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mb/google/hatch: Skip SD card controller WP pin configuration from FSP 

BUG=b:123907904
TEST=SD WP GPIO PAD retains coreboot configuration
     and FSP ScsSdCardWpPinEnabled UPD is set to 0.

Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra 2019-08-16 12:20:01 +05:30 committed by Furquan Shaikh
parent 662c61d449
commit a4542990f4
1 changed files with 2 additions and 0 deletions
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src/mainboard/google/hatch/variants/baseboard/devicetree.cb
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@ -46,6 +46,8 @@ chip soc/intel/cannonlake
register "tcc_offset" = "10" # TCC of 90C
# Unlock GPIO pads
register "PchUnlockGpioPads" = "1"
# SD card WP pin confguration
register "ScsSdCardWpPinEnabled" = "0"
# NOTE: if any variant wants to override this value, use the same format
# as register "common_soc_config.pch_thermal_trip" = "value", instead of