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cpu/x86/smm/smihandler: Apply cosmetic changes 

Use define for SSA base address.
Move EM64T area to 0x7c00 and add reserved area of size 0x100,
as there's no indication that the address 0x7d00 exists on any
platform.

No functional change.

Change-Id: I38c405c8977f5dd571e0da3a44fcad4738b696b2
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Philippe Mathieu-Daudé <philippe.mathieu.daude@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Patrick Rudolph 2017-06-10 08:58:00 +02:00 committed by Martin Roth
parent 1827ec1f4e
commit a4677e426a
2 changed files with 22 additions and 9 deletions
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9
src/cpu/x86/smm/smihandler.c
View File

@ -153,12 +153,14 @@ void smi_handler(u32 smm_revision)
case 0x00030007: case 0x00030007:
state_save.type = LEGACY; state_save.type = LEGACY;
state_save.legacy_state_save = state_save.legacy_state_save =
smm_save_state(smm_base, 0x7e00, node); smm_save_state(smm_base,
SMM_LEGACY_ARCH_OFFSET, node);
break; break;
case 0x00030100: case 0x00030100:
state_save.type = EM64T; state_save.type = EM64T;
state_save.em64t_state_save = state_save.em64t_state_save =
smm_save_state(smm_base, 0x7d00, node); smm_save_state(smm_base,
SMM_EM64T_ARCH_OFFSET, node);
break; break;
case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */ case 0x00030101: /* SandyBridge, IvyBridge, and Haswell */
state_save.type = EM64T101; state_save.type = EM64T101;
@ -169,7 +171,8 @@ void smi_handler(u32 smm_revision)
case 0x00030064: case 0x00030064:
state_save.type = AMD64; state_save.type = AMD64;
state_save.amd64_state_save = state_save.amd64_state_save =
smm_save_state(smm_base, 0x7e00, node); smm_save_state(smm_base,
SMM_AMD64_ARCH_OFFSET, node);
break; break;
default: default:
printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision); printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);

22
src/include/cpu/x86/smm.h
View File

@ -32,6 +32,11 @@
#define SMM_ENTRY_OFFSET 0x8000 #define SMM_ENTRY_OFFSET 0x8000
#define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x)) #define SMM_SAVE_STATE_BEGIN(x) (SMM_ENTRY_OFFSET + (x))
/* AMD64 x86 SMM State-Save Area
* starts @ 0x7e00
*/
#define SMM_AMD64_ARCH_OFFSET 0x7e00
typedef struct { typedef struct {
u16 es_selector; u16 es_selector;
u16 es_attributes; u16 es_attributes;
@ -128,16 +133,20 @@ typedef struct {
/* Intel Core 2 (EM64T) SMM State-Save Area /* Intel Core 2 (EM64T) SMM State-Save Area
* starts @ 0x7d00 * starts @ 0x7c00
*/ */
#define SMM_EM64T_ARCH_OFFSET 0x7c00
#define SMM_EM64T_SAVE_STATE_OFFSET \
SMM_SAVE_STATE_BEGIN(SMM_EM64T_ARCH_OFFSET)
typedef struct { typedef struct {
u8 reserved0[208]; u8 reserved0[256];
u8 reserved1[208];
u32 gdtr_upper_base; u32 gdtr_upper_base;
u32 ldtr_upper_base; u32 ldtr_upper_base;
u32 idtr_upper_base; u32 idtr_upper_base;
u8 reserved1[4]; u8 reserved2[4];
u64 io_rdi; u64 io_rdi;
u64 io_rip; u64 io_rip;
@ -145,13 +154,13 @@ typedef struct {
u64 io_rsi; u64 io_rsi;
u64 cr4; u64 cr4;
u8 reserved2[68]; u8 reserved3[68];
u64 gdtr_base; u64 gdtr_base;
u64 idtr_base; u64 idtr_base;
u64 ldtr_base; u64 ldtr_base;
u8 reserved3[84]; u8 reserved4[84];
u32 smm_revision; u32 smm_revision;
u32 smbase; u32 smbase;
@ -159,7 +168,7 @@ typedef struct {
u16 io_restart; u16 io_restart;
u16 autohalt_restart; u16 autohalt_restart;
u8 reserved4[24]; u8 reserved5[24];
u64 r15; u64 r15;
u64 r14; u64 r14;
@ -394,6 +403,7 @@ typedef struct {
/* Legacy x86 SMM State-Save Area /* Legacy x86 SMM State-Save Area
* starts @ 0x7e00 * starts @ 0x7e00
*/ */
#define SMM_LEGACY_ARCH_OFFSET 0x7e00
typedef struct { typedef struct {
u8 reserved0[248]; u8 reserved0[248];