soc/mediatek/mt8186: Enable USB macro control

When powering down SSUSB, the system needs to wait the ACK from SSUSB.
We found that the setting of USB PAD top macro is not correct and
it will cause timeout waiting for the ACK from SSUSB.

To resolve this, we add mt_pll_set_usb_clock() in pll.c to enable usb
macro control for powering down SSUSB.

TEST=timeout of ssusb powerdown ack does not occur.
BUG=b:239634625

Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Change-Id: I58ba86e0467284e9947bfda1005c151a3e0c8881
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66600
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>

src/soc/mediatek/mt8186/Makefile.inc

@@ -4,6 +4,7 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8186),y)
 all-y += ../common/flash_controller.c
 all-y += ../common/gpio.c ../common/gpio_op.c  gpio.c
 all-y += ../common/i2c.c i2c.c
+all-y += ../common/pll.c pll.c
 all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c
 all-y += ../common/timer.c ../common/timer_prepare.c
 all-y += ../common/uart.c
@@ -12,7 +13,6 @@ bootblock-y += bootblock.c
 bootblock-y += ../common/eint_event.c
 bootblock-y += gic.c
 bootblock-y += ../common/mmu_operations.c
-bootblock-y += ../common/pll.c pll.c
 bootblock-y += ../common/tracker.c ../common/tracker_v1.c
 bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c
 
@@ -23,7 +23,6 @@ romstage-y += emi.c
 romstage-y += ../common/memory.c
 romstage-y += ../common/memory_test.c
 romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c
-romstage-y += ../common/pll.c pll.c
 romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
 romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
 

src/soc/mediatek/mt8186/include/soc/pll.h

@@ -522,4 +522,6 @@ DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_0, 1, 0)
 DEFINE_BITFIELD(INFRACFG_AO_PERI_BUS_REG0_1, 27, 3)
 DEFINE_BIT(INFRACFG_AO_PERI_BUS_REG0_2, 31)
 
+DEFINE_BITFIELD(USB_TOP_CFG_MACRO_CTRL, 1, 0)
+
 #endif /* SOC_MEDIATEK_MT8186_PLL_H */

src/soc/mediatek/mt8186/pll.c

@@ -516,6 +516,12 @@ void mt_pll_raise_cci_freq(u32 freq)
 	clrsetbits32(&mtk_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
 }
 
+void mt_pll_set_usb_clock(void)
+{
+	/* enable usb macro control */
+	SET32_BITFIELDS(&mtk_topckgen->usb_top_cfg, USB_TOP_CFG_MACRO_CTRL, 3);
+}
+
 u32 mt_fmeter_get_freq_khz(enum fmeter_type type, u32 id)
 {
 	u32 output, count, clk_dbg_cfg, clk_misc_cfg_0, clk26cali_0, clk26cali_1;

src/soc/mediatek/mt8186/usb.c

@@ -8,6 +8,7 @@
 #include <device/mmio.h>
 #include <gpio.h>
 #include <soc/gpio.h>
+#include <soc/pll_common.h>
 #include <soc/usb.h>
 
 #define PERI_USB_WAKEUP_DEC_CON1	0x404
@@ -15,6 +16,8 @@
 
 void mtk_usb_prepare(void)
 {
+	mt_pll_set_usb_clock();
+
 	gpio_output(GPIO(USB_DRVVBUS_P1), 1);
 
 	/* disable IP0 debounce */