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soc/qualcomm/ipq40xx: Add coreboot Table entry for serial console 

BUG=chrome-os-partner:49249
TEST=Compiles...
BRANCH=none

Change-Id: I76a24bc9b3cec53d5c10ecd86e5c8e45285e9632
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4ab1717ff020d564abffcee208b6587e1ae2f950
Original-Change-Id: I2d155e80424d1c1837eb35703bd42ff3244e112a
Original-Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/333306
Original-Commit-Ready: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/14662
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Varadarajan Narayanan 2015-10-01 16:12:23 +05:30 committed by Patrick Georgi
parent 4df1e0a2da
commit a486af46b2
1 changed files with 9 additions and 0 deletions
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9
src/soc/qualcomm/ipq40xx/uart.c
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@ -402,5 +402,14 @@ uint8_t uart_rx_byte(int idx)
/* TODO: Implement function */ /* TODO: Implement function */
void uart_fill_lb(void *data) void uart_fill_lb(void *data)
{ {
struct lb_serial serial;
serial.type = LB_SERIAL_TYPE_MEMORY_MAPPED;
serial.baseaddr = (uint32_t)UART1_DM_BASE;
serial.baud = default_baudrate();
serial.regwidth = 1;
lb_add_serial(&serial, data);
lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data);
} }
#endif #endif