diff --git a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
index d72d9767e9..6b3478bdbc 100644
--- a/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
+++ b/src/mainboard/asus/p2b/variants/p3b-f/romstage.c
@@ -25,12 +25,3 @@ void enable_spd(void)
 {
 	outb(0x6f, PM_IO_BASE + 0x37);
 }
-
-/*
- * Disable SPD access after RAM init to allow access to SMBus/I2C offsets
- * 0x48/0x49/0x2d, which is required e.g. by lm-sensors.
- */
-void disable_spd(void)
-{
-	outb(0x67, PM_IO_BASE + 0x37);
-}
diff --git a/src/northbridge/intel/i440bx/raminit.c b/src/northbridge/intel/i440bx/raminit.c
index 80ccaed12b..81c4e785a3 100644
--- a/src/northbridge/intel/i440bx/raminit.c
+++ b/src/northbridge/intel/i440bx/raminit.c
@@ -1001,7 +1001,6 @@ static void sdram_enable(void)
 
 /* Implemented under mainboard. */
 void __weak enable_spd(void) { }
-void __weak disable_spd(void) { }
 
 void sdram_initialize(int s3resume)
 {
@@ -1013,6 +1012,5 @@ void sdram_initialize(int s3resume)
 	sdram_set_spd_registers();
 	sdram_enable();
 
-	disable_spd();
 	timestamp_add_now(TS_INITRAM_END);
 }
diff --git a/src/northbridge/intel/i440bx/raminit.h b/src/northbridge/intel/i440bx/raminit.h
index d2d1729e61..b35554f2e4 100644
--- a/src/northbridge/intel/i440bx/raminit.h
+++ b/src/northbridge/intel/i440bx/raminit.h
@@ -13,7 +13,6 @@
 #define DIMM3		0x53
 
 void enable_spd(void);
-void disable_spd(void);
 void sdram_initialize(int s3resume);
 
 /* Debug */