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update failover handling of some amd64 boards 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1699 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2004-10-21 17:06:49 +00:00
parent dbec2d4090
commit a49f4161f5
7 changed files with 197 additions and 122 deletions
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65
src/mainboard/Iwill/DK8S2/failover.c
View File

@ -3,40 +3,67 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* Make cerain my local apic is useable */
enable_lapic();
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

67
src/mainboard/Iwill/DK8X/failover.c
View File

@ -3,40 +3,67 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* Make cerain my local apic is useable */
enable_lapic();
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain(0);
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

65
src/mainboard/amd/quartet/failover.c
View File

@ -3,40 +3,67 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* Make cerain my local apic is useable */
enable_lapic();
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}

19
src/mainboard/amd/serenade/failover.c
View File

@ -4,22 +4,15 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
@ -60,21 +53,17 @@ static void main(void)
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

19
src/mainboard/amd/solo/failover.c
View File

@ -4,22 +4,15 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
@ -60,21 +53,17 @@ static void main(void)
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

19
src/mainboard/ibm/e325/failover.c
View File

@ -4,22 +4,15 @@
#include <device/pci_ids.h>
#include <arch/io.h>
#include <arch/romcc_io.h>
#include <arch/smp/lapic.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
#define HAVE_REGPARM_SUPPORT 0
#if HAVE_REGPARM_SUPPORT
static unsigned long main(unsigned long bist)
{
#else
static void main(void)
{
unsigned long bist = 0;
#endif
/* Make cerain my local apic is useable */
enable_lapic();
@ -60,21 +53,17 @@ static void main(void)
goto fallback_image;
}
normal_image:
asm("jmp __normal_image"
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm("jmp __cpu_reset"
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
#if HAVE_REGPARM_SUPPORT
return bist;
#else
return;
#endif
}

65
src/mainboard/newisys/khepri/failover.c
View File

@ -3,40 +3,67 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <arch/io.h>
#include "arch/romcc_io.h"
#include <arch/romcc_io.h>
#include <cpu/x86/lapic.h>
#include "pc80/mc146818rtc_early.c"
#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
#include "northbridge/amd/amdk8/early_ht.c"
#include "cpu/p6/boot_cpu.c"
#include "cpu/x86/lapic/boot_cpu.c"
#include "northbridge/amd/amdk8/reset_test.c"
static void main(void)
static unsigned long main(unsigned long bist)
{
/* Make cerain my local apic is useable */
enable_lapic();
/* Is this a cpu only reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto cpu_reset;
}
}
/* Is this a secondary cpu? */
if (!boot_cpu()) {
if (last_boot_normal()) {
goto normal_image;
} else {
goto fallback_image;
}
}
/* Nothing special needs to be done to find bus 0 */
/* Allow the HT devices to be found */
enumerate_ht_chain();
/* Setup the 8111 */
amd8111_enable_rom();
/* Is this a cpu reset? */
if (cpu_init_detected()) {
if (last_boot_normal()) {
asm("jmp __normal_image");
} else {
asm("jmp __cpu_reset");
}
}
/* Is this a deliberate reset by the bios */
else if (bios_reset_detected() && last_boot_normal()) {
asm("jmp __normal_image");
}
/* Is this a secondary cpu? */
else if (!boot_cpu() && last_boot_normal()) {
asm("jmp __normal_image");
if (bios_reset_detected() && last_boot_normal()) {
goto normal_image;
}
/* This is the primary cpu how should I boot? */
else if (do_normal_boot()) {
asm("jmp __normal_image");
goto normal_image;
}
else {
goto fallback_image;
}
normal_image:
asm volatile ("jmp __normal_image"
: /* outputs */
: "a" (bist) /* inputs */
: /* clobbers */
);
cpu_reset:
asm volatile ("jmp __cpu_reset"
: /* outputs */
: "a"(bist) /* inputs */
: /* clobbers */
);
fallback_image:
return bist;
}