diff --git a/src/mainboard/dmp/vortex86ex/Kconfig b/src/mainboard/dmp/vortex86ex/Kconfig
index 723a251cf1..b1db0dc481 100644
--- a/src/mainboard/dmp/vortex86ex/Kconfig
+++ b/src/mainboard/dmp/vortex86ex/Kconfig
@@ -50,6 +50,11 @@ config ID_SECTION_OFFSET
 	hex
 	default 0x4800
 
+# SPI I/O base address control.
+config I2C_BASE
+	hex
+	default 0xfb00
+
 # ROM Strap PLL config setting :
 
 choice
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.c b/src/southbridge/dmp/vortex86ex/southbridge.c
index 5be857582b..bcdd8b22b5 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.c
+++ b/src/southbridge/dmp/vortex86ex/southbridge.c
@@ -72,6 +72,7 @@ static const unsigned char irq_to_int_routing[16] = {
 #define PIDE_IRQ 5
 
 #define SPI1_IRQ 10
+#define I2C0_IRQ 10
 #define MOTOR_IRQ 11
 
 /* RT0-3 IRQs. */
@@ -429,6 +430,16 @@ static void ex_sb_uart_init(struct device *dev)
 	//pci_write_config16(SB, SB_REG_UART_CFG_IO_BASE, 0x0);
 }
 
+static void i2c_init(struct device *dev)
+{
+	u8 mapped_irq = irq_to_int_routing[I2C0_IRQ];
+	u32 cfg = 0;
+	cfg |= 1 << 31;			// UE = enabled.
+	cfg |= (mapped_irq << 16);	// IIRT0.
+	cfg |= CONFIG_I2C_BASE;		// UIOA.
+	pci_write_config32(dev, SB_REG_II2CCR, cfg);
+}
+
 static int get_rtc_update_in_progress(void)
 {
 	if (cmos_read(RTC_REG_A) & RTC_UIP)
@@ -547,6 +558,9 @@ static void vortex86_sb_read_resources(device_t dev)
 
 	/* Reserve space for flash */
 	vortex86_sb_set_spi_flash_size(dev, 2, flash_size);
+
+	/* Reserve space for I2C */
+	vortex86_sb_set_io_resv(dev, 3, CONFIG_I2C_BASE, 8);
 }
 
 static void southbridge_init_func1(struct device *dev)
@@ -577,6 +591,7 @@ static void southbridge_init(struct device *dev)
 	if (dev->device == 0x6011) {
 		ex_sb_gpio_init(dev);
 		ex_sb_uart_init(dev);
+		i2c_init(dev);
 	}
 	pci_routing_fixup(dev);
 
diff --git a/src/southbridge/dmp/vortex86ex/southbridge.h b/src/southbridge/dmp/vortex86ex/southbridge.h
index 0cc28facb6..316d30a2fc 100644
--- a/src/southbridge/dmp/vortex86ex/southbridge.h
+++ b/src/southbridge/dmp/vortex86ex/southbridge.h
@@ -36,6 +36,7 @@
 #define	SB_REG_IPFCR		0xc0
 #define	SB_REG_FRWPR		0xc4
 #define	SB_REG_STRAP		0xce
+#define	SB_REG_II2CCR		0xd4
 
 #define	SB1			PCI_DEV(0, 7, 1)
 #define	SB1_REG_EXT_PIRQ_ROUTE2	0xb4