GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/siemens/mc_apl6: Enable SDHCI and disable eMMC controller 

This mainboard variant uses SD-card and not eMMC. Therefore eMMC
controller is disabled while SDHCI is enabled.

Change-Id: I40b314905730b5d74c674d2251f8a4e5c807805f
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36676
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Werner Zeh 2019-11-08 11:49:01 +01:00 committed by Patrick Georgi
parent 4f7fe494a0
commit a4b7befbd5
1 changed files with 2 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

36
src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
View File

@ -14,38 +14,6 @@ chip soc/intel/apollolake
register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[4]" = "CLKREQ_DISABLED"
register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED" register "pcie_rp_clkreq_pin[5]" = "CLKREQ_DISABLED"
# EMMC TX DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [14:8] steps of delay for HS400, each 125ps.
# [6:0] steps of delay for SDR104/HS200, each 125ps.
register "emmc_tx_data_cntl1" = "0x0C16"
# EMMC TX DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_tx_data_cntl2" = "0x28162828"
# EMMC RX CMD/DATA Delay 1
# Refer to EDS-Vol2-22.3.
# [30:24] steps of delay for SDR50, each 125ps.
# [22:16] steps of delay for DDR50, each 125ps.
# [14:8] steps of delay for SDR25/HS50, each 125ps.
# [6:0] steps of delay for SDR12, each 125ps.
register "emmc_rx_cmd_data_cntl1" = "0x00181717"
# EMMC RX CMD/DATA Delay 2
# Refer to EDS-Vol2-22.3.
# [17:16] stands for Rx Clock before Output Buffer
# [14:8] steps of delay for Auto Tuning Mode, each 125ps.
# [6:0] steps of delay for HS200, each 125ps.
register "emmc_rx_cmd_data_cntl2" = "0x10008"
# 0:HS400(Default), 1:HS200, 2:DDR50
register "emmc_host_max_speed" = "1"
device domain 0 on device domain 0 on
device pci 00.0 on end # - Host Bridge device pci 00.0 on end # - Host Bridge
device pci 00.1 off end # - DPTF device pci 00.1 off end # - DPTF
@ -97,8 +65,8 @@ chip soc/intel/apollolake
device pci 19.1 off end # - SPI 1 device pci 19.1 off end # - SPI 1
device pci 19.2 off end # - SPI 2 device pci 19.2 off end # - SPI 2
device pci 1a.0 off end # - PWM device pci 1a.0 off end # - PWM
device pci 1b.0 off end # - SDCARD device pci 1b.0 on end # - SDCARD
device pci 1c.0 on end # - eMMC device pci 1c.0 off end # - eMMC
device pci 1d.0 off end # - UFS device pci 1d.0 off end # - UFS
device pci 1e.0 off end # - SDIO device pci 1e.0 off end # - SDIO
device pci 1f.0 on end # - LPC device pci 1f.0 on end # - LPC