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Make timer2 the default choice for TSC initialization. 

For boards where timer2 is unusable, there's still the IO based
initialization available using the Kconfig option TSC_CALIBRATE_WITH_IO

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Kevin O'Connor <kevin@koconnor.net>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5787 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-09-08 10:58:02 +00:00
parent 24f83a76ae
commit a4c0a1d6e6
3 changed files with 4 additions and 11 deletions
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2
src/cpu/x86/Kconfig
View File

@ -19,7 +19,7 @@ config UDELAY_TSC
bool
default n
config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
config TSC_CALIBRATE_WITH_IO
bool
default n

4
src/cpu/x86/tsc/delay_tsc.c
View File

@ -7,7 +7,7 @@
static unsigned long clocks_per_usec;
#if (CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 == 1)
#if !CONFIG_TSC_CALIBRATE_WITH_IO
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
/* ------ Calibrate the TSC -------
@ -82,7 +82,7 @@ bad_ctc:
return 0;
}
#else /* CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2 */
#else /* CONFIG_TSC_CALIBRATE_WITH_IO */
/*
* this is the "no timer2" version.

9
src/southbridge/amd/cs5536/Kconfig
View File

@ -19,12 +19,5 @@
config SOUTHBRIDGE_AMD_CS5536
bool
select TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
config UDELAY_TSC
bool
default y
depends on SOUTHBRIDGE_AMD_CS5536
select UDELAY_TSC