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soc/mediatek/mt8192: Add PLL and clock init support 

Add PLL and clock init code.

TEST=Boots correctly on MT8192EVB.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Change-Id: Ia49342c058577e8e107b7e56c867bf21532e40d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Weiyi Lu 2020-05-13 10:01:14 +08:00 committed by Hung-Te Lin
parent 8fcc246a56
commit a4cad368a2
6 changed files with 2201 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/mediatek/common/include/soc/pll_common.h
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@ -20,6 +20,8 @@
struct mux {
void *reg;
void *set_reg;
void *clr_reg;
void *upd_reg;
u8 mux_shift;
u8 mux_width;

12
src/soc/mediatek/common/pll.c
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@ -12,9 +12,15 @@ void mux_set_sel(const struct mux *mux, u32 sel)
u32 mask = GENMASK(mux->mux_width - 1, 0);
u32 val = read32(mux->reg);
val &= ~(mask << mux->mux_shift);
val |= (sel & mask) << mux->mux_shift;
write32(mux->reg, val);
if (mux->set_reg && mux->clr_reg) {
write32(mux->clr_reg, mask << mux->mux_shift);
write32(mux->set_reg, sel << mux->mux_shift);
} else {
val &= ~(mask << mux->mux_shift);
val |= (sel & mask) << mux->mux_shift;
write32(mux->reg, val);
}
if (mux->upd_reg)
write32(mux->upd_reg, 1 << mux->upd_shift);
}

419
src/soc/mediatek/mt8192/include/soc/infracfg.h Normal file
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@ -0,0 +1,419 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_MT8192_INFRACFG_H
#define SOC_MEDIATEK_MT8192_INFRACFG_H
#include <soc/addressmap.h>
#include <types.h>
struct mt8192_infracfg_regs {
u32 reserved1[20];
u32 infra_globalcon_dcmctl; /* 0x0050 */
u32 reserved2[7];
u32 infra_bus_dcm_ctrl; /* 0x0070 */
u32 peri_bus_dcm_ctrl;
u32 mem_dcm_ctrl;
u32 dfs_mem_dcm_ctrl;
u32 module_sw_cg_0_set;
u32 module_sw_cg_0_clr;
u32 module_sw_cg_1_set;
u32 module_sw_cg_1_clr;
u32 module_sw_cg_0_sta;
u32 module_sw_cg_1_sta;
u32 module_clk_sel;
u32 mem_cg_ctrl;
u32 p2p_rx_clk_on;
u32 module_sw_cg_2_set;
u32 module_sw_cg_2_clr;
u32 module_sw_cg_2_sta;
u32 reserved3[1];
u32 dramc_wbr; /* 0x00b4 */
u32 reserved4[2];
u32 module_sw_cg_3_set; /* 0x00c0 */
u32 module_sw_cg_3_clr;
u32 module_sw_cg_3_sta;
u32 reserved5[5];
u32 module_sw_cg_4_set; /* 0x00e0 */
u32 module_sw_cg_4_clr;
u32 module_sw_cg_4_sta;
u32 reserved6[5];
u32 i2c_dbtool_misc; /* 0x0100 */
u32 md_sleep_ctrl_mask;
u32 pmicw_clock_ctrl;
u32 reserved7[5];
u32 infra_globalcon_rst0_set; /* 0x0120 */
u32 infra_globalcon_rst0_clr;
u32 infra_globalcon_rst0_sta;
u32 reserved8[1];
u32 infra_globalcon_rst1_set; /* 0x0130 */
u32 infra_globalcon_rst1_clr;
u32 infra_globalcon_rst1_sta;
u32 reserved9[1];
u32 infra_globalcon_rst2_set; /* 0x0140 */
u32 infra_globalcon_rst2_clr;
u32 infra_globalcon_rst2_sta;
u32 reserved10[1];
u32 infra_globalcon_rst3_set; /* 0x0150 */
u32 infra_globalcon_rst3_clr;
u32 infra_globalcon_rst3_sta;
u32 reserved11[41];
u32 infra_topaxi_si0_ctl; /* 0x0200 */
u32 infra_topaxi_si1_ctl;
u32 infra_topaxi_mdbus_ctl;
u32 infra_mci_si0_ctl;
u32 infra_mci_si1_ctl;
u32 infra_mci_si2_ctl;
u32 infra_mci_async_ctl;
u32 infra_mci_cg_mfg_sec_sta;
u32 infra_topaxi_protecten;
u32 infra_topaxi_protecten_sta0;
u32 infra_topaxi_protecten_sta1;
u32 reserved12[1];
u32 infra_apb_async_sta; /* 0x0230 */
u32 infra_topaxi_si2_ctl;
u32 infra_topaxi_fmem_mdhw_ctrl;
u32 infra_conn_gals_ctl;
u32 infra_mci_trans_con_read;
u32 infra_mci_trans_con_write;
u32 infra_mci_id_remap_con;
u32 infra_mci_emi_trans_con;
u32 infra_topaxi_protecten_1;
u32 infra_topaxi_protecten_sta0_1;
u32 infra_topaxi_protecten_sta1_1;
u32 reserved13[1];
u32 infra_topaxi_aslice_ctrl; /* 0x0260 */
u32 infra_topaxi_aslice_ctrl_1;
u32 infra_topaxi_aslice_ctrl_2;
u32 infra_topaxi_aslice_ctrl_3;
u32 infra_topaxi_mi_ctrl;
u32 infra_topaxi_cbip_aslice_ctrl;
u32 infra_topaxi_cbip_slice_ctrl;
u32 infra_top_master_sideband;
u32 infra_ssusb_dev;
u32 reserved14[1];
u32 infra_topaxi_emi_gmc_l2c_ctrl; /* 0x0288 */
u32 infra_topaxi_cbip_slice_ctrl_1;
u32 infra_mfg_slave_gals_ctrl;
u32 infra_mfg_master_m0_gals_ctrl;
u32 infra_mfg_master_m1_gals_ctrl;
u32 infra_top_master_sideband_1;
u32 infra_topaxi_protecten_set;
u32 infra_topaxi_protecten_clr;
u32 infra_topaxi_protecten_1_set;
u32 infra_topaxi_protecten_1_clr;
u32 infra_topaxi_cbip_slice_ctrl_2;
u32 reserved15[1];
u32 infra_topaxi_aslice_ctrl_4; /* 0x02b8 */
u32 reserved16[1];
u32 infra_topaxi_protecten_mcu; /* 0x02c0 */
u32 infra_topaxi_protecten_mcu_set;
u32 infra_topaxi_protecten_mcu_clr;
u32 reserved17[1];
u32 infra_topaxi_protecten_mm; /* 0x02d0 */
u32 infra_topaxi_protecten_mm_set;
u32 infra_topaxi_protecten_mm_clr;
u32 reserved18[1];
u32 infra_topaxi_protecten_mcu_sta0; /* 0x02e0 */
u32 infra_topaxi_protecten_mcu_sta1;
u32 infra_topaxi_protecten_mm_sta0;
u32 infra_topaxi_protecten_mm_sta1;
u32 reserved19[1];
u32 infra_apu_master_m0_gals_ctl; /* 0x02f4 */
u32 infra_apu_master_m1_gals_ctl;
u32 infra_topaxi_bus_dbg_con_ao;
u32 md1_bank0_map0;
u32 md1_bank0_map1;
u32 md1_bank0_map2;
u32 md1_bank0_map3;
u32 md1_bank1_map0;
u32 md1_bank1_map1;
u32 md1_bank1_map2;
u32 md1_bank1_map3;
u32 md1_bank4_map0;
u32 md1_bank4_map1;
u32 md1_bank4_map2;
u32 md1_bank4_map3;
u32 md2_bank0_map0;
u32 md2_bank0_map1;
u32 md2_bank0_map2;
u32 md2_bank0_map3;
u32 reserved20[4];
u32 md2_bank4_map0; /* 0x0350 */
u32 md2_bank4_map1;
u32 md2_bank4_map2;
u32 md2_bank4_map3;
u32 c2k_config;
u32 c2k_status;
u32 c2k_spm_ctrl;
u32 reserved21[1];
u32 ap2md_dummy; /* 0x0370 */
u32 reserved22[3];
u32 conn_map0; /* 0x0380 */
u32 cldma_map0;
u32 conn_map1;
u32 conn_bus_con;
u32 mcusys_dfd_map;
u32 conn_map2;
u32 conn_map3;
u32 conn_map4;
u32 module_clk_sel_set;
u32 module_clk_sel_clr;
u32 pmicw_clock_ctrl_set;
u32 pmicw_clock_ctrl_clr;
u32 dramc_wbr_set;
u32 dramc_wbr_clr;
u32 topaxi_si0_ctl_set;
u32 topaxi_si0_ctl_clr;
u32 topaxi_si1_ctl_set;
u32 topaxi_si1_ctl_clr;
u32 reserved23[14];
u32 peri_cci_sideband_con; /* 0x0400 */
u32 mfg_cci_sideband_con;
u32 reserved24[2];
u32 infra_pwm_cksw_ctrl; /* 0x0410 */
u32 reserved25[59];
u32 infra_ao_dbg_con0; /* 0x0500 */
u32 infra_ao_dbg_con1;
u32 infra_ao_dbg_con2;
u32 infra_ao_dbg_con3;
u32 md_dbg_ck_con;
u32 infra_ao_dbg_sta;
u32 reserved26[58];
u32 mfg_misc_con; /* 0x0600 */
u32 reserved27[63];
u32 infra_rsvd0; /* 0x0700 */
u32 infra_rsvd1;
u32 infra_rsvd2;
u32 infra_rsvd3;
u32 infra_topaxi_protecten_2;
u32 infra_topaxi_protecten_set_2;
u32 infra_topaxi_protecten_clr_2;
u32 reserved28[1];
u32 infra_topaxi_protecten_sta0_2; /* 0x0720 */
u32 infra_topaxi_protecten_sta1_2;
u32 reserved29[2];
u32 infra_globalcon_rst4_set; /* 0x0730 */
u32 infra_globalcon_rst4_clr;
u32 infra_globalcon_rst4_sta;
u32 infra_ao_sec_rst_con4;
u32 reserved30[16];
u32 mcu2emi_m0_parity; /* 0x0780 */
u32 mcu2emi_m0_parity_dbg_aw_1;
u32 mcu2emi_m0_parity_dbg_aw_2;
u32 mcu2emi_m0_parity_dbg_ar_1;
u32 mcu2emi_m0_parity_dbg_ar_2;
u32 mcu2emi_m1_parity;
u32 mcu2emi_m1_parity_dbg_aw_1;
u32 mcu2emi_m1_parity_dbg_aw_2;
u32 mcu2emi_m1_parity_dbg_ar_1;
u32 mcu2emi_m1_parity_dbg_ar_2;
u32 mcu2ifr_reg_parity;
u32 mcu2ifr_reg_parity_dbg_aw_1;
u32 mcu2ifr_reg_parity_dbg_aw_2;
u32 mcu2ifr_reg_parity_dbg_ar_1;
u32 mcu2ifr_reg_parity_dbg_ar_2;
u32 ifr_l3c2mcu_parity;
u32 ifr_l3c2mcu_parity_dbg_r_1;
u32 reserved31[47];
u32 md1_sbc_key0; /* 0x0880 */
u32 md1_sbc_key1;
u32 md1_sbc_key2;
u32 md1_sbc_key3;
u32 md1_sbc_key4;
u32 md1_sbc_key5;
u32 md1_sbc_key6;
u32 md1_sbc_key7;
u32 md1_sbc_key_lock;
u32 reserved32[1];
u32 md1_misc_lock; /* 0x08a8 */
u32 md1_misc;
u32 c2k_sbc_key0;
u32 c2k_sbc_key1;
u32 c2k_sbc_key2;
u32 c2k_sbc_key3;
u32 c2k_sbc_key4;
u32 c2k_sbc_key5;
u32 c2k_sbc_key6;
u32 c2k_sbc_key7;
u32 c2k_sbc_key_lock;
u32 reserved33[11];
u32 infra_bonding; /* 0x0900 */
u32 reserved34[63];
u32 infra_ao_scpsys_apb_async_sta; /* 0x0a00 */
u32 infra_ao_md32_tx_apb_async_sta;
u32 infra_ao_md32_rx_apb_async_sta;
u32 infra_ao_cksys_apb_async_sta;
u32 infra_ao_pmic_wrap_tx_apb_async_sta;
u32 infra_mcu2apu_asl0_ctl;
u32 infra_mcu2reg_asl0_ctl;
u32 infra_mcu_decoder_infra_ctl;
u32 infra_mcu_decoder_sta0;
u32 infra_mcu_decoder_sta1;
u32 infra_idle_async_bit_en_0;
u32 infra_apu_slave_gals_ctrl;
u32 infra_aximem_idle_bit_en_0;
u32 infra_mcu_path_sync_ctl;
u32 infra_conn2ap_int_mask;
u32 infra_mcu_pwr_ctl_mask;
u32 infra_md_rsv;
u32 reserved35[7];
u32 infra_mem_26m_cksel; /* 0x0a60 */
u32 reserved36[39];
u32 pll_ulposc_con0; /* 0x0b00 */
u32 pll_ulposc_con1;
u32 reserved37[2];
u32 pll_auxadc_con0; /* 0x0b10 */
u32 scp_infra_irq_set;
u32 scp_infra_irq_clr;
u32 scp_infra_ctrl;
u32 reserved38[24];
u32 infra_topaxi_protecten_vdnr; /* 0x0b80 */
u32 infra_topaxi_protecten_vdnr_set;
u32 infra_topaxi_protecten_vdnr_clr;
u32 infra_topaxi_protecten_vdnr_sta0;
u32 infra_topaxi_protecten_vdnr_sta1;
u32 reserved39[3];
u32 infra_topaxi_protecten_vdnr_1; /* 0x0ba0 */
u32 infra_topaxi_protecten_vdnr_set_1;
u32 infra_topaxi_protecten_vdnr_clr_1;
u32 infra_topaxi_protecten_vdnr_sta0_1;
u32 infra_topaxi_protecten_vdnr_sta1_1;
u32 reserved40[19];
u32 cldma_ctrl; /* 0x0c00 */
u32 reserved41[63];
u32 infrabus_dbg0; /* 0x0d00 */
u32 infrabus_dbg1;
u32 infrabus_dbg2;
u32 infrabus_dbg3;
u32 infrabus_dbg4;
u32 infrabus_dbg5;
u32 infrabus_dbg6;
u32 infrabus_dbg7;
u32 infrabus_dbg8;
u32 infrabus_dbg9;
u32 infrabus_dbg10;
u32 infrabus_dbg11;
u32 infrabus_dbg12;
u32 infrabus_dbg13;
u32 infrabus_dbg14;
u32 infrabus_dbg15;
u32 infrabus_dbg16;
u32 infrabus_dbg17;
u32 infrabus_dbg18;
u32 infrabus_dbg19;
u32 infrabus_dbg20;
u32 infrabus_dbg21;
u32 infrabus_dbg22;
u32 infrabus_dbg23;
u32 infrabus_dbg24;
u32 infrabus_dbg25;
u32 infrabus_dbg26;
u32 infrabus_dbg27;
u32 infrabus_dbg28;
u32 infrabus_dbg29;
u32 infrabus_dbg30;
u32 infrabus_dbg31;
u32 infrabus_dbg32;
u32 infrabus_dbg33;
u32 infrabus_dbg34;
u32 infrabus_dbg35;
u32 infrabus_dbg36;
u32 infrabus_dbg37;
u32 infrabus_dbg38;
u32 infrabus_dbg39;
u32 infrabus_dbg40;
u32 infrabus_dbg41;
u32 infrabus_dbg42;
u32 infrabus_dbg43;
u32 infrabus_dbg44;
u32 infrabus_dbg45;
u32 reserved42[4];
u32 infra_topaxi_protecten_mm_2; /* 0x0dc8 */
u32 infra_topaxi_protecten_mm_set_2;
u32 infra_topaxi_protecten_mm_clr_2;
u32 infra_topaxi_protecten_mm_sta0_2;
u32 infra_topaxi_protecten_mm_sta1_2;
u32 reserved43[5];
u32 infrabus_dbg_mask2; /* 0x0df0 */
u32 reserved44[19];
u32 infra_ao_sec_mm0; /* 0x0e40 */
u32 infra_ao_sec_mm1;
u32 infra_ao_sec_mm2;
u32 infra_ao_sec_mm3;
u32 infra_ao_sec_mm4;
u32 infra_ao_sec_mm5;
u32 infra_ao_sec_mm6;
u32 infra_ao_sec_mm7;
u32 infra_ao_sec_mm8;
u32 infra_ao_sec_mm9;
u32 infra_ao_sec_mm10;
u32 infra_ao_sec_mm11;
u32 infra_ao_sec_mm12;
u32 infra_ao_sec_mm13;
u32 infra_ao_sec_mm14;
u32 infra_ao_sec_mm15;
u32 infra_ao_sec_mm16;
u32 reserved45[5];
u32 infra_ao_mm_hang_free; /* 0x0e98 */
u32 infra_ao_module_hang_free;
u32 reserved46[24];
u32 infra_misc; /* 0x0f00 */
u32 infra_acp;
u32 misc_config;
u32 infra_misc2;
u32 mdsys_misc_con;
u32 reserved47[27];
u32 infra_ao_sec_con; /* 0x0f80 */
u32 infra_ao_sec_cg_con0;
u32 infra_ao_sec_cg_con1;
u32 infra_ao_sec_rst_con0;
u32 infra_ao_sec_rst_con1;
u32 infra_ao_sec_rst_con2;
u32 reserved48[1];
u32 infra_ao_sec_cg_con2; /* 0x0f9c */
u32 infra_ao_sec_rst_con3;
u32 infra_ao_sec_cg_con3;
u32 reserved49[2];
u32 infra_ao_sec_hyp; /* 0x0fb0 */
u32 infra_ao_sec_mfg_hyp;
};
check_member(mt8192_infracfg_regs, infra_globalcon_dcmctl, 0x0050);
check_member(mt8192_infracfg_regs, infra_bus_dcm_ctrl, 0x0070);
check_member(mt8192_infracfg_regs, module_sw_cg_3_set, 0x00c0);
check_member(mt8192_infracfg_regs, module_sw_cg_4_set, 0x00e0);
check_member(mt8192_infracfg_regs, i2c_dbtool_misc, 0x0100);
check_member(mt8192_infracfg_regs, infra_globalcon_rst0_set, 0x0120);
check_member(mt8192_infracfg_regs, infra_topaxi_si0_ctl, 0x0200);
check_member(mt8192_infracfg_regs, md2_bank4_map0, 0x0350);
check_member(mt8192_infracfg_regs, conn_map0, 0x0380);
check_member(mt8192_infracfg_regs, peri_cci_sideband_con, 0x0400);
check_member(mt8192_infracfg_regs, infra_pwm_cksw_ctrl, 0x0410);
check_member(mt8192_infracfg_regs, infra_ao_dbg_con0, 0x0500);
check_member(mt8192_infracfg_regs, mfg_misc_con, 0x0600);
check_member(mt8192_infracfg_regs, infra_rsvd0, 0x0700);
check_member(mt8192_infracfg_regs, infra_globalcon_rst4_set, 0x0730);
check_member(mt8192_infracfg_regs, mcu2emi_m0_parity, 0x0780);
check_member(mt8192_infracfg_regs, md1_sbc_key0, 0x0880);
check_member(mt8192_infracfg_regs, infra_bonding, 0x0900);
check_member(mt8192_infracfg_regs, infra_ao_scpsys_apb_async_sta, 0x0a00);
check_member(mt8192_infracfg_regs, infra_mem_26m_cksel, 0x0a60);
check_member(mt8192_infracfg_regs, pll_ulposc_con0, 0x0b00);
check_member(mt8192_infracfg_regs, pll_auxadc_con0, 0x0b10);
check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr, 0x0b80);
check_member(mt8192_infracfg_regs, infra_topaxi_protecten_vdnr_1, 0x0ba0);
check_member(mt8192_infracfg_regs, cldma_ctrl, 0x0c00);
check_member(mt8192_infracfg_regs, infrabus_dbg0, 0x0d00);
check_member(mt8192_infracfg_regs, infra_topaxi_protecten_mm_2, 0x0dc8);
check_member(mt8192_infracfg_regs, infrabus_dbg_mask2, 0x0df0);
check_member(mt8192_infracfg_regs, infra_ao_sec_mm0, 0x0e40);
check_member(mt8192_infracfg_regs, infra_ao_mm_hang_free, 0x0e98);
check_member(mt8192_infracfg_regs, infra_misc, 0x0f00);
check_member(mt8192_infracfg_regs, infra_ao_sec_con, 0x0f80);
check_member(mt8192_infracfg_regs, infra_ao_sec_hyp, 0x0fb0);
check_member(mt8192_infracfg_regs, infra_ao_sec_mfg_hyp, 0x0fb4);
static struct mt8192_infracfg_regs *const mt8192_infracfg =
(void *)INFRACFG_AO_BASE;
#endif /* SOC_MEDIATEK_MT8192_INFRACFG_H */

1038
src/soc/mediatek/mt8192/include/soc/mcucfg.h Normal file
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297
src/soc/mediatek/mt8192/include/soc/pll.h Normal file
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@ -0,0 +1,297 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef SOC_MEDIATEK_MT8192_PLL_H
#define SOC_MEDIATEK_MT8192_PLL_H
#include <device/mmio.h>
#include <types.h>
#include <soc/pll_common.h>
struct mtk_topckgen_regs {
u32 clk_mode;
u32 clk_cfg_update;
u32 clk_cfg_update1;
u32 clk_cfg_update2;
u32 clk_cfg_0;
u32 clk_cfg_0_set;
u32 clk_cfg_0_clr;
u32 reserved1[1];
u32 clk_cfg_1; /* 0x0020 */
u32 clk_cfg_1_set;
u32 clk_cfg_1_clr;
u32 reserved2[1];
u32 clk_cfg_2; /* 0x0030 */
u32 clk_cfg_2_set;
u32 clk_cfg_2_clr;
u32 reserved3[1];
u32 clk_cfg_3; /* 0x0040 */
u32 clk_cfg_3_set;
u32 clk_cfg_3_clr;
u32 reserved4[1];
u32 clk_cfg_4; /* 0x0050 */
u32 clk_cfg_4_set;
u32 clk_cfg_4_clr;
u32 reserved5[1];
u32 clk_cfg_5; /* 0x0060 */
u32 clk_cfg_5_set;
u32 clk_cfg_5_clr;
u32 reserved6[1];
u32 clk_cfg_6; /* 0x0070 */
u32 clk_cfg_6_set;
u32 clk_cfg_6_clr;
u32 reserved7[1];
u32 clk_cfg_7; /* 0x0080 */
u32 clk_cfg_7_set;
u32 clk_cfg_7_clr;
u32 reserved8[1];
u32 clk_cfg_8; /* 0x0090 */
u32 clk_cfg_8_set;
u32 clk_cfg_8_clr;
u32 reserved9[1];
u32 clk_cfg_9; /* 0x00a0 */
u32 clk_cfg_9_set;
u32 clk_cfg_9_clr;
u32 reserved10[1];
u32 clk_cfg_10; /* 0x00b0 */
u32 clk_cfg_10_set;
u32 clk_cfg_10_clr;
u32 reserved11[1];
u32 clk_cfg_11; /* 0x00c0 */
u32 clk_cfg_11_set;
u32 clk_cfg_11_clr;
u32 reserved12[1];
u32 clk_cfg_12; /* 0x00d0 */
u32 clk_cfg_12_set;
u32 clk_cfg_12_clr;
u32 reserved13[1];
u32 clk_cfg_13; /* 0x00e0 */
u32 clk_cfg_13_set;
u32 clk_cfg_13_clr;
u32 reserved14[1];
u32 clk_cfg_14; /* 0x00f0 */
u32 clk_cfg_14_set;
u32 clk_cfg_14_clr;
u32 reserved15[1];
u32 clk_cfg_15; /* 0x0100 */
u32 clk_cfg_15_set;
u32 clk_cfg_15_clr;
u32 reserved16[1];
u32 clk_cfg_16; /* 0x0110 */
u32 clk_cfg_16_set;
u32 clk_cfg_16_clr;
u32 reserved17[9];
u32 clk_misc_cfg_0; /* 0x0140 */
u32 reserved18[3];
u32 clk_misc_cfg_1; /* 0x0150 */
u32 reserved19[10];
u32 clk_dbg_cfg; /* 0x017c */
u32 reserved20[32];
u32 clk_scp_cfg_0; /* 0x0200 */
u32 reserved21[3];
u32 clk_scp_cfg_1; /* 0x0210 */
u32 reserved22[3];
u32 clk26cali_0; /* 0x0220 */
u32 clk26cali_1;
u32 reserved23[2];
u32 cksta_reg; /* 0x0230 */
u32 cksta_reg1;
u32 cksta_reg2;
u32 reserved24[49];
u32 clkmon_clk_sel_reg; /* 0x0300 */
u32 clkmon_k1_reg;
u32 reserved25[6];
u32 clk_auddiv_0; /* 0x0320 */
u32 clk_auddiv_1;
u32 clk_auddiv_2;
u32 aud_top_cfg;
u32 aud_top_mon;
u32 clk_auddiv_3;
u32 clk_auddiv_4;
u32 reserved26[113];
u32 clk_extck_reg; /* 0x0500 */
};
check_member(mtk_topckgen_regs, clk_misc_cfg_0, 0x0140);
check_member(mtk_topckgen_regs, clk_misc_cfg_1, 0x0150);
check_member(mtk_topckgen_regs, clk_dbg_cfg, 0x017c);
check_member(mtk_topckgen_regs, clk_scp_cfg_0, 0x0200);
check_member(mtk_topckgen_regs, clk_scp_cfg_1, 0x0210);
check_member(mtk_topckgen_regs, clk26cali_0, 0x0220);
check_member(mtk_topckgen_regs, cksta_reg, 0x0230);
check_member(mtk_topckgen_regs, clkmon_clk_sel_reg, 0x0300);
check_member(mtk_topckgen_regs, clk_auddiv_0, 0x0320);
check_member(mtk_topckgen_regs, clk_extck_reg, 0x0500);
struct mtk_apmixed_regs {
u32 ap_pll_con0;
u32 ap_pll_con1;
u32 ap_pll_con2;
u32 ap_pll_con3;
u32 ap_pll_con4;
u32 ap_pll_con5;
u32 clksq_stb_con0;
u32 pll_pwr_con0;
u32 pll_pwr_con1;
u32 pll_iso_con0;
u32 pll_iso_con1;
u32 pll_stb_con0;
u32 div_stb_con0;
u32 pll_chg_con0;
u32 pll_test_con0;
u32 pll_test_con1;
u32 apll1_tuner_con0;
u32 apll2_tuner_con0;
u32 reserved0[2];
u32 pllon_con0;
u32 pllon_con1;
u32 pllon_con2;
u32 pllon_con3;
u32 reserved1[104];
u32 ap_pllgp1_con0; /* 0x0200 */
u32 ap_pllgp1_con1;
u32 armpll_ll_con0;
u32 armpll_ll_con1;
u32 armpll_ll_con2;
u32 armpll_ll_con3;
u32 armpll_bl0_con0;
u32 armpll_bl_con1;
u32 armpll_bl_con2;
u32 armpll_bl_con3;
u32 armpll_bl1_con0;
u32 armpll_bl1_con1;
u32 armpll_bl1_con2;
u32 armpll_bl1_con3;
u32 armpll_bl2_con0;
u32 armpll_bl2_con1;
u32 armpll_bl2_con2;
u32 armpll_bl2_con3;
u32 armpll_bl3_con0;
u32 armpll_bl3_con1;
u32 armpll_bl3_con2;
u32 armpll_bl3_con3;
u32 ccipll_con0;
u32 ccipll_con1;
u32 ccipll_con2;
u32 ccipll_con3;
u32 mfgpll_con0;
u32 mfgpll_con1;
u32 mfgpll_con2;
u32 mfgpll_con3;
u32 ap_pllgp1_con2;
u32 reserved2[33];
u32 ap_pllgp2_con0; /* 0x0300 */
u32 ap_pllgp2_con1;
u32 univpll_con0;
u32 univpll_con1;
u32 univpll_con2;
u32 univpll_con3;
u32 apll1_con0;
u32 apll1_con1;
u32 apll1_con2;
u32 apll1_con3;
u32 apll1_con4;
u32 apll2_con0;
u32 apll2_con1;
u32 apll2_con2;
u32 apll2_con3;
u32 apll2_con4;
u32 mainpll_con0;
u32 mainpll_con1;
u32 mainpll_con2;
u32 mainpll_con3;
u32 msdcpll_con0;
u32 msdcpll_con1;
u32 msdcpll_con2;
u32 msdcpll_con3;
u32 mmpll_con0;
u32 mmpll_con1;
u32 mmpll_con2;
u32 mmpll_con3;
u32 adsppll_con0;
u32 adsppll_con1;
u32 adsppll_con2;
u32 adsppll_con3;
u32 tvdpll_con0;
u32 tvdpll_con1;
u32 tvdpll_con2;
u32 tvdpll_con3;
u32 mpll_con0;
u32 mpll_con1;
u32 mpll_con2;
u32 mpll_con3;
u32 apupll_con0;
u32 apupll_con1;
u32 apupll_con2;
u32 apupll_con3;
u32 ap_pllgp3_con0;
u32 npupll_con0;
u32 npupll_con1;
u32 npupll_con2;
u32 npupll_con3;
u32 usbpll_con0;
u32 usbpll_con1;
u32 usbpll_con2;
};
check_member(mtk_apmixed_regs, ap_pllgp1_con0, 0x0200);
check_member(mtk_apmixed_regs, ap_pllgp2_con0, 0x0300);
check_member(mtk_apmixed_regs, usbpll_con2, 0x03cc);
enum {
USBPLL_EN = 0x1 << 2,
PLL_DIV_EN = 0xff << 24,
};
enum {
MCU_DIV_MASK = 0x1f << 17,
MCU_DIV_1 = 0x8 << 17,
MCU_MUX_MASK = 0x3 << 9,
MCU_MUX_SRC_PLL = 0x1 << 9,
};
enum {
PLL_PWR_ON_DELAY = 30,
PLL_ISO_DELAY = 1,
PLL_EN_DELAY = 20,
};
enum {
PCW_INTEGER_BITS = 8,
};
/* PLL rate */
enum {
ARMPLL_LL_HZ = 1075 * MHz,
ARMPLL_BL_HZ = 774 * MHz,
CCIPLL_HZ = 730 * MHz,
MAINPLL_HZ = 2184UL * MHz,
UNIVPLL_HZ = 2496UL * MHz,
USBPLL_HZ = 192UL * 13 * MHz,
MSDCPLL_HZ = 384 * MHz,
MMPLL_HZ = 2750UL * MHz,
ADSPPLL_HZ = 750 * MHz,
MFGPLL_HZ = 358 * MHz,
TVDPLL_HZ = 594 * MHz,
APLL1_HZ = 180633600,
APLL2_HZ = 196608 * KHz,
};
/* top_div rate */
enum {
CLK26M_HZ = 26 * MHz,
MAINPLL_D5_HZ = MAINPLL_HZ / 5,
MAINPLL_D5_D4_HZ = MAINPLL_D5_HZ / 4,
};
/* top_mux rate */
enum {
SPI_HZ = MAINPLL_D5_D4_HZ,
UART_HZ = CLK26M_HZ,
};
DEFINE_BITFIELD(PLLGP1_LVRREF, 18, 17)
DEFINE_BITFIELD(PLLGP2_LVRREF, 10, 9)
#endif /* SOC_MEDIATEK_MT8192_PLL_H */

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src/soc/mediatek/mt8192/pll.c Normal file
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/* SPDX-License-Identifier: GPL-2.0-only */
#include <device/mmio.h>
#include <delay.h>
#include <stddef.h>
#include <soc/addressmap.h>
#include <soc/infracfg.h>
#include <soc/mcucfg.h>
#include <soc/pll.h>
enum mux_id {
TOP_AXI_SEL,
TOP_SPM_SEL,
TOP_SCP_SEL,
TOP_BUS_AXIMEM_SEL,
TOP_DISP_SEL,
TOP_MDP_SEL,
TOP_IMG1_SEL,
TOP_IMG2_SEL,
TOP_IPE_SEL,
TOP_DPE_SEL,
TOP_CAM_SEL,
TOP_CCU_SEL,
TOP_DSP_SEL,
TOP_DSP7_SEL,
TOP_MFG_REF_SEL,
TOP_MFG_PLL_SEL,
TOP_CAMTG_SEL,
TOP_CAMTG2_SEL,
TOP_CAMTG3_SEL,
TOP_CAMTG4_SEL,
TOP_CAMTG5_SEL,
TOP_CAMTG6_SEL,
TOP_UART_SEL,
TOP_SPI_SEL,
TOP_MSDC50_0_HCLK_SEL,
TOP_MSDC50_0_SEL,
TOP_MSDC30_1_SEL,
TOP_MSDC30_2_SEL,
TOP_AUDIO_SEL,
TOP_AUD_INTBUS_SEL,
TOP_PWRAP_ULPOSC_SEL,
TOP_ATB_SEL,
TOP_PWRMCU_SEL,
TOP_DPI_SEL,
TOP_SCAM_SEL,
TOP_DISP_PWM_SEL,
TOP_USB_TOP_SEL,
TOP_SSUSB_XHCI_SEL,
TOP_I2C_SEL,
TOP_SENINF_SEL,
TOP_SENINF1_SEL,
TOP_SENINF2_SEL,
TOP_SENINF3_SEL,
TOP_TL_SEL,
TOP_DXCC_SEL,
TOP_AUD_ENGEN1_SEL,
TOP_AUD_ENGEN2_SEL,
TOP_AES_UFSFDE_SEL,
TOP_UFS_SEL,
TOP_AUD_1_SEL,
TOP_AUD_2_SEL,
TOP_ADSP_SEL,
TOP_DPMAIF_MAIN_SEL,
TOP_VENC_SEL,
TOP_VDEC_SEL,
TOP_CAMTM_SEL,
TOP_PWM_SEL,
TOP_AUDIO_H_SEL,
TOP_SPMI_MST_SEL,
TOP_DVFSRC_SEL,
TOP_AES_MSDCFDE_SEL,
TOP_MCUPM_SEL,
TOP_SFLASH_SEL,
TOP_NR_MUX
};
#define MUX(_id, _reg, _mux_shift, _mux_width) \
[_id] = { \
.reg = &mtk_topckgen->_reg, \
.set_reg = &mtk_topckgen->_reg##_set, \
.clr_reg = &mtk_topckgen->_reg##_clr, \
.mux_shift = _mux_shift, \
.mux_width = _mux_width, \
.upd_reg = NULL, \
.upd_shift = 0, \
}
#define MUX_UPD(_id, _reg, _mux_shift, _mux_width, _upd_reg, _upd_shift)\
[_id] = { \
.reg = &mtk_topckgen->_reg, \
.set_reg = &mtk_topckgen->_reg##_set, \
.clr_reg = &mtk_topckgen->_reg##_clr, \
.mux_shift = _mux_shift, \
.mux_width = _mux_width, \
.upd_reg = &mtk_topckgen->_upd_reg, \
.upd_shift = _upd_shift, \
}
static const struct mux muxes[] = {
/* CLK_CFG_0 */
MUX_UPD(TOP_AXI_SEL, clk_cfg_0, 0, 3, clk_cfg_update, 0),
MUX_UPD(TOP_SPM_SEL, clk_cfg_0, 8, 2, clk_cfg_update, 1),
MUX_UPD(TOP_SCP_SEL, clk_cfg_0, 16, 3, clk_cfg_update, 2),
MUX_UPD(TOP_BUS_AXIMEM_SEL, clk_cfg_0, 24, 3, clk_cfg_update, 3),
/* CLK_CFG_1 */
MUX_UPD(TOP_DISP_SEL, clk_cfg_1, 0, 4, clk_cfg_update, 4),
MUX_UPD(TOP_MDP_SEL, clk_cfg_1, 8, 4, clk_cfg_update, 5),
MUX_UPD(TOP_IMG1_SEL, clk_cfg_1, 16, 4, clk_cfg_update, 6),
MUX_UPD(TOP_IMG2_SEL, clk_cfg_1, 24, 4, clk_cfg_update, 7),
/* CLK_CFG_2 */
MUX_UPD(TOP_IPE_SEL, clk_cfg_2, 0, 4, clk_cfg_update, 8),
MUX_UPD(TOP_DPE_SEL, clk_cfg_2, 8, 3, clk_cfg_update, 9),
MUX_UPD(TOP_CAM_SEL, clk_cfg_2, 16, 4, clk_cfg_update, 10),
MUX_UPD(TOP_CCU_SEL, clk_cfg_2, 24, 4, clk_cfg_update, 11),
/* CLK_CFG_3 */
MUX_UPD(TOP_DSP_SEL, clk_cfg_3, 0, 3, clk_cfg_update, 12),
/* CLK_CFG_4 */
MUX_UPD(TOP_DSP7_SEL, clk_cfg_4, 0, 3, clk_cfg_update, 16),
MUX_UPD(TOP_MFG_REF_SEL, clk_cfg_4, 16, 2, clk_cfg_update, 18),
MUX(TOP_MFG_PLL_SEL, clk_cfg_4, 18, 1),
MUX_UPD(TOP_CAMTG_SEL, clk_cfg_4, 24, 3, clk_cfg_update, 19),
/* CLK_CFG_5 */
MUX_UPD(TOP_CAMTG2_SEL, clk_cfg_5, 0, 3, clk_cfg_update, 20),
MUX_UPD(TOP_CAMTG3_SEL, clk_cfg_5, 8, 3, clk_cfg_update, 21),
MUX_UPD(TOP_CAMTG4_SEL, clk_cfg_5, 16, 3, clk_cfg_update, 22),
MUX_UPD(TOP_CAMTG5_SEL, clk_cfg_5, 24, 3, clk_cfg_update, 23),
/* CLK_CFG_6 */
MUX_UPD(TOP_CAMTG6_SEL, clk_cfg_6, 0, 3, clk_cfg_update, 24),
MUX_UPD(TOP_UART_SEL, clk_cfg_6, 8, 1, clk_cfg_update, 25),
MUX_UPD(TOP_SPI_SEL, clk_cfg_6, 16, 2, clk_cfg_update, 26),
MUX_UPD(TOP_MSDC50_0_HCLK_SEL, clk_cfg_6, 24, 2, clk_cfg_update, 27),
/* CLK_CFG_7 */
MUX_UPD(TOP_MSDC50_0_SEL, clk_cfg_7, 0, 3, clk_cfg_update, 28),
MUX_UPD(TOP_MSDC30_1_SEL, clk_cfg_7, 8, 3, clk_cfg_update, 29),
MUX_UPD(TOP_MSDC30_2_SEL, clk_cfg_7, 16, 3, clk_cfg_update, 30),
MUX_UPD(TOP_AUDIO_SEL, clk_cfg_7, 24, 2, clk_cfg_update1, 0),
/* CLK_CFG_8 */
MUX_UPD(TOP_AUD_INTBUS_SEL, clk_cfg_8, 0, 2, clk_cfg_update1, 1),
MUX_UPD(TOP_PWRAP_ULPOSC_SEL, clk_cfg_8, 8, 3, clk_cfg_update1, 2),
MUX_UPD(TOP_ATB_SEL, clk_cfg_8, 16, 2, clk_cfg_update1, 3),
MUX_UPD(TOP_PWRMCU_SEL, clk_cfg_8, 24, 3, clk_cfg_update1, 4),
/* CLK_CFG_9 */
MUX_UPD(TOP_DPI_SEL, clk_cfg_9, 0, 3, clk_cfg_update1, 5),
MUX_UPD(TOP_SCAM_SEL, clk_cfg_9, 8, 1, clk_cfg_update1, 6),
MUX_UPD(TOP_DISP_PWM_SEL, clk_cfg_9, 16, 3, clk_cfg_update1, 7),
MUX_UPD(TOP_USB_TOP_SEL, clk_cfg_9, 24, 2, clk_cfg_update1, 8),
/* CLK_CFG_10 */
MUX_UPD(TOP_SSUSB_XHCI_SEL, clk_cfg_10, 0, 2, clk_cfg_update1, 9),
MUX_UPD(TOP_I2C_SEL, clk_cfg_10, 8, 2, clk_cfg_update1, 10),
MUX_UPD(TOP_SENINF_SEL, clk_cfg_10, 16, 3, clk_cfg_update1, 11),
MUX_UPD(TOP_SENINF1_SEL, clk_cfg_10, 24, 3, clk_cfg_update1, 12),
/* CLK_CFG_11 */
MUX_UPD(TOP_SENINF2_SEL, clk_cfg_11, 0, 3, clk_cfg_update1, 13),
MUX_UPD(TOP_SENINF3_SEL, clk_cfg_11, 8, 3, clk_cfg_update1, 14),
MUX_UPD(TOP_TL_SEL, clk_cfg_11, 16, 2, clk_cfg_update1, 15),
MUX_UPD(TOP_DXCC_SEL, clk_cfg_11, 24, 2, clk_cfg_update1, 16),
/* CLK_CFG_12 */
MUX_UPD(TOP_AUD_ENGEN1_SEL, clk_cfg_12, 0, 2, clk_cfg_update1, 17),
MUX_UPD(TOP_AUD_ENGEN2_SEL, clk_cfg_12, 8, 2, clk_cfg_update1, 18),
MUX_UPD(TOP_AES_UFSFDE_SEL, clk_cfg_12, 16, 3, clk_cfg_update1, 19),
MUX_UPD(TOP_UFS_SEL, clk_cfg_12, 24, 3, clk_cfg_update1, 20),
/* CLK_CFG_13 */
MUX_UPD(TOP_AUD_1_SEL, clk_cfg_13, 0, 1, clk_cfg_update1, 21),
MUX_UPD(TOP_AUD_2_SEL, clk_cfg_13, 8, 1, clk_cfg_update1, 22),
MUX_UPD(TOP_ADSP_SEL, clk_cfg_13, 16, 3, clk_cfg_update1, 23),
MUX_UPD(TOP_DPMAIF_MAIN_SEL, clk_cfg_13, 24, 3, clk_cfg_update1, 24),
/* CLK_CFG_14 */
MUX_UPD(TOP_VENC_SEL, clk_cfg_14, 0, 4, clk_cfg_update1, 25),
MUX_UPD(TOP_VDEC_SEL, clk_cfg_14, 8, 4, clk_cfg_update1, 26),
MUX_UPD(TOP_CAMTM_SEL, clk_cfg_14, 16, 2, clk_cfg_update1, 27),
MUX_UPD(TOP_PWM_SEL, clk_cfg_14, 24, 1, clk_cfg_update1, 28),
/* CLK_CFG_15 */
MUX_UPD(TOP_AUDIO_H_SEL, clk_cfg_15, 0, 2, clk_cfg_update1, 29),
MUX_UPD(TOP_SPMI_MST_SEL, clk_cfg_15, 8, 3, clk_cfg_update1, 30),
MUX_UPD(TOP_DVFSRC_SEL, clk_cfg_15, 16, 1, clk_cfg_update2, 0),
MUX_UPD(TOP_AES_MSDCFDE_SEL, clk_cfg_15, 24, 3, clk_cfg_update2, 1),
/* CLK_CFG_16 */
MUX_UPD(TOP_MCUPM_SEL, clk_cfg_16, 0, 2, clk_cfg_update2, 2),
MUX_UPD(TOP_SFLASH_SEL, clk_cfg_16, 8, 2, clk_cfg_update2, 3),
};
struct mux_sel {
enum mux_id id;
u32 sel;
};
static const struct mux_sel mux_sels[] = {
/* CLK_CFG_0 */
{ .id = TOP_AXI_SEL, .sel = 2 }, /* 2: mainpll_d7_d2 */
{ .id = TOP_SPM_SEL, .sel = 2 }, /* 2: mainpll_d7_d4 */
{ .id = TOP_SCP_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_BUS_AXIMEM_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
/* CLK_CFG_1 */
{ .id = TOP_DISP_SEL, .sel = 8 }, /* 8: mainpll_d4 */
{ .id = TOP_MDP_SEL, .sel = 8 }, /* 8: tvdpll_ck */
{ .id = TOP_IMG1_SEL, .sel = 1 }, /* 1: univpll_d4 */
{ .id = TOP_IMG2_SEL, .sel = 1 }, /* 1: univpll_d4 */
/* CLK_CFG_2 */
{ .id = TOP_IPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */
{ .id = TOP_DPE_SEL, .sel = 1 }, /* 1: mainpll_d4 */
{ .id = TOP_CAM_SEL, .sel = 3 }, /* 3: univpll_d4 */
{ .id = TOP_CCU_SEL, .sel = 8 }, /* 8: univpll_d5 */
/* CLK_CFG_3 */
{ .id = TOP_DSP_SEL, .sel = 1 }, /* 1: univpll_d6_d2 */
/* CLK_CFG_4 */
{ .id = TOP_DSP7_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
{ .id = TOP_MFG_REF_SEL, .sel = 3 }, /* 3: mainpll_d5_d2 */
{ .id = TOP_MFG_PLL_SEL, .sel = 1 }, /* 1: mfgpll */
{ .id = TOP_CAMTG_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */
/* CLK_CFG_5 */
{ .id = TOP_CAMTG2_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */
{ .id = TOP_CAMTG3_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */
{ .id = TOP_CAMTG4_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */
{ .id = TOP_CAMTG5_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */
/* CLK_CFG_6 */
{ .id = TOP_CAMTG6_SEL, .sel = 1 }, /* 1: univpll_192m_d8 */
{ .id = TOP_UART_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_SPI_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */
{ .id = TOP_MSDC50_0_HCLK_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
/* CLK_CFG_7 */
{ .id = TOP_MSDC50_0_SEL, .sel = 1 }, /* 1: msdcpll_ck */
{ .id = TOP_MSDC30_1_SEL, .sel = 4 }, /* 4: msdcpll_d2 */
{ .id = TOP_MSDC30_2_SEL, .sel = 4 }, /* 4: msdcpll_d2 */
{ .id = TOP_AUDIO_SEL, .sel = 0 }, /* 0: clk26m */
/* CLK_CFG_8 */
{ .id = TOP_AUD_INTBUS_SEL, .sel = 1 }, /* 1: mainpll_d4_d4 */
{ .id = TOP_PWRAP_ULPOSC_SEL, .sel = 0 }, /* 0: osc_d10 */
{ .id = TOP_ATB_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
{ .id = TOP_PWRMCU_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */
/* CLK_CFG_9 */
{ .id = TOP_DPI_SEL, .sel = 1 }, /* 1: tvdpll_d2 */
{ .id = TOP_SCAM_SEL, .sel = 1 }, /* 1: mainpll_d5_d4 */
{ .id = TOP_DISP_PWM_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_USB_TOP_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
/* CLK_CFG_10 */
{ .id = TOP_SSUSB_XHCI_SEL, .sel = 1 }, /* 1: univpll_d5_d4 */
{ .id = TOP_I2C_SEL, .sel = 2 }, /* 2: univpll_d5_d4 */
{ .id = TOP_SENINF_SEL, .sel = 4 }, /* 4: univpll_d7 */
{ .id = TOP_SENINF1_SEL, .sel = 4 }, /* 4: univpll_d7 */
/* CLK_CFG_11 */
{ .id = TOP_SENINF2_SEL, .sel = 4 }, /* 4: univpll_d7 */
{ .id = TOP_SENINF3_SEL, .sel = 4 }, /* 4: univpll_d7 */
{ .id = TOP_TL_SEL, .sel = 1 }, /* 1: univpll_192m_d2 */
{ .id = TOP_DXCC_SEL, .sel = 1 }, /* 1: mainpll_d4_d2 */
/* CLK_CFG_12 */
{ .id = TOP_AUD_ENGEN1_SEL, .sel = 2 }, /* 2: apll1_d4 */
{ .id = TOP_AUD_ENGEN2_SEL, .sel = 2 }, /* 2: apll2_d4 */
{ .id = TOP_AES_UFSFDE_SEL, .sel = 6 }, /* 6: univpll_d6 */
{ .id = TOP_UFS_SEL, .sel = 6 }, /* 6: msdcpll_d2 */
/* CLK_CFG_13 */
{ .id = TOP_AUD_1_SEL, .sel = 1 }, /* 1: apll1_ck */
{ .id = TOP_AUD_2_SEL, .sel = 1 }, /* 1: apll2_ck */
{ .id = TOP_ADSP_SEL, .sel = 7 }, /* 7: adsppll_ck */
{ .id = TOP_DPMAIF_MAIN_SEL, .sel = 3 }, /* 3: mainpll_d4_d2 */
/* CLK_CFG_14 */
{ .id = TOP_VENC_SEL, .sel = 14 }, /* 14: univpll_d5_d2 */
{ .id = TOP_VDEC_SEL, .sel = 4 }, /* 4: mainpll_d5_d2 */
{ .id = TOP_CAMTM_SEL, .sel = 2 }, /* 2: univpll_d6_d2 */
{ .id = TOP_PWM_SEL, .sel = 0 }, /* 0: clk26m */
/* CLK_CFG_15 */
{ .id = TOP_AUDIO_H_SEL, .sel = 3 }, /* 3: apll2_ck */
{ .id = TOP_SPMI_MST_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_DVFSRC_SEL, .sel = 0 }, /* 0: clk26m */
{ .id = TOP_AES_MSDCFDE_SEL, .sel = 5 }, /* 5: univpll_d6 */
/* CLK_CFG_16 */
{ .id = TOP_MCUPM_SEL, .sel = 2 }, /* 2: mainpll_d6_d2 */
{ .id = TOP_SFLASH_SEL, .sel = 1 }, /* 1: mainpll_d7_d8 */
};
enum pll_id {
APMIXED_ARMPLL_LL,
APMIXED_ARMPLL_BL,
APMIXED_CCIPLL,
APMIXED_MAINPLL,
APMIXED_UNIVPLL,
APMIXED_USBPLL,
APMIXED_MSDCPLL,
APMIXED_MMPLL,
APMIXED_ADSPPLL,
APMIXED_MFGPLL,
APMIXED_TVDPLL,
APMIXED_APLL1,
APMIXED_APLL2,
APMIXED_PLL_MAX
};
const u32 pll_div_rate[] = {
3800UL * MHz,
1900 * MHz,
950 * MHz,
475 * MHz,
237500 * KHz,
0,
};
static const struct pll plls[] = {
PLL(APMIXED_ARMPLL_LL, armpll_ll_con0, armpll_ll_con3,
NO_RSTB_SHIFT, 22, armpll_ll_con1, 24, armpll_ll_con1, 0,
pll_div_rate),
PLL(APMIXED_ARMPLL_BL, armpll_bl0_con0, armpll_bl_con3,
NO_RSTB_SHIFT, 22, armpll_bl_con1, 24, armpll_bl_con1, 0,
pll_div_rate),
PLL(APMIXED_CCIPLL, ccipll_con0, ccipll_con3,
NO_RSTB_SHIFT, 22, ccipll_con1, 24, ccipll_con1, 0,
pll_div_rate),
PLL(APMIXED_MAINPLL, mainpll_con0, mainpll_con3,
23, 22, mainpll_con1, 24, mainpll_con1, 0,
pll_div_rate),
PLL(APMIXED_UNIVPLL, univpll_con0, univpll_con3,
23, 22, univpll_con1, 24, univpll_con1, 0,
pll_div_rate),
PLL(APMIXED_USBPLL, usbpll_con0, usbpll_con2,
NO_RSTB_SHIFT, 22, usbpll_con0, 24, usbpll_con0, 0,
pll_div_rate),
PLL(APMIXED_MSDCPLL, msdcpll_con0, msdcpll_con3,
NO_RSTB_SHIFT, 22, msdcpll_con1, 24, msdcpll_con1, 0,
pll_div_rate),
PLL(APMIXED_MMPLL, mmpll_con0, mmpll_con3,
23, 22, mmpll_con1, 24, mmpll_con1, 0,
pll_div_rate),
PLL(APMIXED_ADSPPLL, adsppll_con0, adsppll_con3,
NO_RSTB_SHIFT, 22, adsppll_con1, 24, adsppll_con1, 0,
pll_div_rate),
PLL(APMIXED_MFGPLL, mfgpll_con0, mfgpll_con3,
NO_RSTB_SHIFT, 22, mfgpll_con1, 24, mfgpll_con1, 0,
pll_div_rate),
PLL(APMIXED_TVDPLL, tvdpll_con0, tvdpll_con3,
NO_RSTB_SHIFT, 22, tvdpll_con1, 24, tvdpll_con1, 0,
pll_div_rate),
PLL(APMIXED_APLL1, apll1_con0, apll1_con4,
NO_RSTB_SHIFT, 32, apll1_con1, 24, apll1_con2, 0,
pll_div_rate),
PLL(APMIXED_APLL2, apll2_con0, apll2_con4,
NO_RSTB_SHIFT, 32, apll2_con1, 24, apll2_con2, 0,
pll_div_rate),
};
struct rate {
enum pll_id id;
u32 rate;
};
static const struct rate rates[] = {
{ .id = APMIXED_ARMPLL_LL, .rate = ARMPLL_LL_HZ },
{ .id = APMIXED_ARMPLL_BL, .rate = ARMPLL_BL_HZ },
{ .id = APMIXED_CCIPLL, .rate = CCIPLL_HZ },
{ .id = APMIXED_MAINPLL, .rate = MAINPLL_HZ },
{ .id = APMIXED_UNIVPLL, .rate = UNIVPLL_HZ },
{ .id = APMIXED_USBPLL, .rate = USBPLL_HZ },
{ .id = APMIXED_MSDCPLL, .rate = MSDCPLL_HZ },
{ .id = APMIXED_MMPLL, .rate = MMPLL_HZ },
{ .id = APMIXED_ADSPPLL, .rate = ADSPPLL_HZ },
{ .id = APMIXED_MFGPLL, .rate = MFGPLL_HZ },
{ .id = APMIXED_TVDPLL, .rate = TVDPLL_HZ },
{ .id = APMIXED_APLL1, .rate = APLL1_HZ },
{ .id = APMIXED_APLL2, .rate = APLL2_HZ },
};
void pll_set_pcw_change(const struct pll *pll)
{
setbits32(pll->div_reg, PLL_PCW_CHG);
}
void mt_pll_init(void)
{
int i;
/* enable clock square1 low-pass filter */
setbits32(&mtk_apmixed->ap_pll_con0, 0x2);
/* reduce PLL current */
SET32_BITFIELDS(&mtk_apmixed->ap_pllgp1_con1, PLLGP1_LVRREF, 1);
SET32_BITFIELDS(&mtk_apmixed->ap_pllgp2_con1, PLLGP2_LVRREF, 1);
/* xPLL PWR ON */
for (i = 0; i < APMIXED_PLL_MAX; i++)
setbits32(plls[i].pwr_reg, PLL_PWR_ON);
udelay(PLL_PWR_ON_DELAY);
/* xPLL ISO Disable */
for (i = 0; i < APMIXED_PLL_MAX; i++)
clrbits32(plls[i].pwr_reg, PLL_ISO);
udelay(PLL_ISO_DELAY);
/* xPLL Frequency Set */
for (i = 0; i < ARRAY_SIZE(rates); i++)
pll_set_rate(&plls[rates[i].id], rates[i].rate);
/* xPLL Frequency Enable */
for (i = 0; i < APMIXED_PLL_MAX; i++) {
if (i == APMIXED_USBPLL)
setbits32(plls[APMIXED_USBPLL].pwr_reg, USBPLL_EN);
else
setbits32(plls[i].reg, PLL_EN);
}
/* wait for PLL stable */
udelay(PLL_EN_DELAY);
/* xPLL DIV Enable & RSTB */
for (i = 0; i < APMIXED_PLL_MAX; i++) {
if (plls[i].rstb_shift != NO_RSTB_SHIFT) {
setbits32(plls[i].reg, PLL_DIV_EN);
setbits32(plls[i].reg, 1 << plls[i].rstb_shift);
}
}
/* MCUCFG CLKMUX */
clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_DIV_MASK, MCU_DIV_1);
clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_DIV_MASK, MCU_DIV_1);
clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_DIV_MASK, MCU_DIV_1);
clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg0, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
clrsetbits32(&mt8192_mcucfg->cpu_plldiv_cfg1, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
clrsetbits32(&mt8192_mcucfg->bus_plldiv_cfg, MCU_MUX_MASK, MCU_MUX_SRC_PLL);
/* enable infrasys DCM */
setbits32(&mt8192_infracfg->infra_bus_dcm_ctrl, 0x3 << 21);
/* initialize SPM request */
setbits32(&mtk_topckgen->clk_scp_cfg_0, 0x3ff);
clrsetbits32(&mtk_topckgen->clk_scp_cfg_1, 0x100c, 0x3);
/*
* TOP CLKMUX -- DO NOT CHANGE WITHOUT ADJUSTING <soc/pll.h> CONSTANTS!
*/
for (i = 0; i < ARRAY_SIZE(mux_sels); i++)
mux_set_sel(&muxes[mux_sels[i].id], mux_sels[i].sel);
/* enable [14] dramc_pll104m_ck */
setbits32(&mtk_topckgen->clk_misc_cfg_0, 1 << 14);
}