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Documentation: x86 MTRR setup, TempRamExit and MTRR loading 

Document how to test TempRamExit and verify the MTRR setup and loading.

TEST=None

Change-Id: I57a604fa139edac4b05453547d3caf185db491e0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14113
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy 2016-01-31 12:19:13 -08:00 committed by Martin Roth
parent b953d05e60
commit a4d8180913
1 changed files with 16 additions and 0 deletions
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16
Documentation/Intel/development.html
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@ -97,6 +97,7 @@
<li>Disable the <li>Disable the
<a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a>
</li> </li>
<li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li>
<li> <li>
Implement the .init routine for the Implement the .init routine for the
<a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a>
@ -115,6 +116,7 @@
Implement the Implement the
<a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a> <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a>
</li> </li>
<li>coreboot should now attempt to load the payload</li>
</ol> </ol>
@ -184,6 +186,20 @@
</td> </td>
<td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td> <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td>
</tr> </tr>
<tr>
<td>MTRRs</td>
<td>
Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/stack.c;hb=HEAD#l42">setup_stack_and_mtrrs</a><br>
Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l71">after_raminit.S</a>
</td>
<td>Set: Post code 0x91
(<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l213">POST_FSP_TEMP_RAM_EXIT</a>)
is displayed by
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l41">after_raminit.S</a><br>
Load: Post code 0x3C is displayed by
<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/intel/fsp1_1/after_raminit.S;hb=HEAD#l152">after_raminit.S</a><br>
and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td>
</tr>
<tr> <tr>
<td>PCI Device Support</td> <td>PCI Device Support</td>
<td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td> <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td>