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src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers 

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes HAOUAS 2020-08-11 09:39:43 +02:00 committed by Patrick Georgi
parent a3022056a2
commit a4dd33cc8b
12 changed files with 35 additions and 24 deletions
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5
src/drivers/aspeed/common/ast_main.c
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@ -4,6 +4,7 @@
*/
#include <delay.h>
#include <device/pci_def.h>
#include "ast_drv.h"
#include "ast_dram_tables.h"
@ -329,7 +330,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
ast->dev = dev;
/* PCI BAR 1 */
res = find_resource(dev->pdev, 0x14);
res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1);
if (!res) {
dev_err(dev->pdev, "BAR1 resource not found.\n");
ret = -EIO;
@ -343,7 +344,7 @@ int ast_driver_load(struct drm_device *dev, unsigned long flags)
/* PCI BAR 2 */
ast->io_space_uses_mmap = false;
res = find_resource(dev->pdev, 0x18);
res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2);
if (!res) {
dev_err(dev->pdev, "BAR2 resource not found.\n");
ret = -EIO;

3
src/drivers/aspeed/common/ast_mode_corebootfb.c
View File

@ -3,6 +3,7 @@
* Copied from Linux drivers/gpu/drm/ast/ast_mode.c
*/
#include <edid.h>
#include <device/pci_def.h>
#include "ast_drv.h"
@ -18,7 +19,7 @@ int ast_crtc_do_set_base(struct drm_crtc *crtc)
struct drm_framebuffer *fb = crtc->primary->fb;
/* PCI BAR 0 */
struct resource *res = find_resource(crtc->dev->pdev, 0x10);
struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
if (!res) {
printk(BIOS_ERR, "BAR0 resource not found.\n");
return -EIO;

2
src/drivers/uart/oxpcie.c
View File

@ -12,7 +12,7 @@ static void oxford_oxpcie_enable(struct device *dev)
{
printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");
struct resource *res = find_resource(dev, 0x10);
struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!res) {
printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
return;

7
src/northbridge/intel/pineview/gma.c
View File

@ -6,6 +6,7 @@
#include <delay.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <drivers/intel/gma/i915_reg.h>
@ -234,9 +235,9 @@ static void gma_func0_init(struct device *dev)
int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;
/* Find base addresses */
mmio_res = find_resource(dev, 0x10);
gtt_res = find_resource(dev, 0x1c);
pio_res = find_resource(dev, 0x14);
mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
gtt_res = find_resource(dev, PCI_BASE_ADDRESS_3);
pio_res = find_resource(dev, PCI_BASE_ADDRESS_1);
physbase = pci_read_config32(dev, 0x5c) & ~0xf;
if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {

5
src/southbridge/intel/bd82x6x/smbus.c
View File

@ -4,6 +4,7 @@
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
@ -34,7 +35,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
@ -47,7 +48,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, val);
}

3
src/southbridge/intel/common/pciehp.c
View File

@ -5,6 +5,7 @@
#include <acpi/acpigen.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include "pciehp.h"
@ -121,7 +122,7 @@ static void slot_dev_read_resources(struct device *dev)
{
struct resource *resource;
resource = new_resource(dev, 0x10);
resource = new_resource(dev, PCI_BASE_ADDRESS_0);
resource->size = 1 << 23;
resource->align = 22;
resource->gran = 22;

9
src/southbridge/intel/i82801gx/smbus.c
View File

@ -4,6 +4,7 @@
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/smbus_host.h>
#include "i82801gx.h"
@ -16,7 +17,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
@ -29,7 +30,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 data)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, data);
}
@ -41,7 +42,7 @@ static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes, const u8 *bu
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
@ -53,7 +54,7 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_block_read(res->base, device, cmd, bytes, buf);
}

3
src/southbridge/intel/i82801gx/usb_ehci.c
View File

@ -7,6 +7,7 @@
#include "i82801gx.h"
#include <device/pci_ehci.h>
#include <device/mmio.h>
#include <device/pci_def.h>
#include <device/pci_ops.h>
static void usb_ehci_init(struct device *dev)
@ -23,7 +24,7 @@ static void usb_ehci_init(struct device *dev)
pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17));
/* Clear any pending port changes */
res = find_resource(dev, 0x10);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
base = res2mmio(res, 0, 0);
reg32 = read32(base + 0x24) | (1 << 2);
write32(base + 0x24, reg32);

5
src/southbridge/intel/i82801ix/smbus.c
View File

@ -4,6 +4,7 @@
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
@ -23,7 +24,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
@ -36,7 +37,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, val);
}

9
src/southbridge/intel/i82801jx/smbus.c
View File

@ -4,6 +4,7 @@
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
@ -23,7 +24,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
@ -36,7 +37,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, val);
}
@ -50,7 +51,7 @@ static int lsmbus_block_write(struct device *dev, u8 cmd, u8 bytes,
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_block_write(res->base, device, cmd, bytes, buf);
}
@ -62,7 +63,7 @@ static int lsmbus_block_read(struct device *dev, u8 cmd, u8 bytes, u8 *buf)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_block_read(res->base, device, cmd, bytes, buf);
}

5
src/southbridge/intel/ibexpeak/smbus.c
View File

@ -4,6 +4,7 @@
#include <device/path.h>
#include <device/smbus.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <device/smbus_host.h>
@ -33,7 +34,7 @@ static int lsmbus_read_byte(struct device *dev, u8 address)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_read_byte(res->base, device, address);
}
@ -46,7 +47,7 @@ static int lsmbus_write_byte(struct device *dev, u8 address, u8 val)
device = dev->path.i2c.device;
pbus = get_pbus_smbus(dev);
res = find_resource(pbus->dev, 0x20);
res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
return do_smbus_write_byte(res->base, device, address, val);
}

3
src/southbridge/intel/ibexpeak/thermal.c
View File

@ -3,6 +3,7 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include "pch.h"
#include <device/mmio.h>
@ -13,7 +14,7 @@ static void thermal_init(struct device *dev)
u8 *base;
printk(BIOS_DEBUG, "Thermal init start.\n");
res = find_resource(dev, 0x10);
res = find_resource(dev, PCI_BASE_ADDRESS_0);
if (!res)
return;