diff --git a/src/mainboard/emulation/qemu-i440fx/northbridge.c b/src/mainboard/emulation/qemu-i440fx/northbridge.c
index f975b6cdc4..c08d59e795 100644
--- a/src/mainboard/emulation/qemu-i440fx/northbridge.c
+++ b/src/mainboard/emulation/qemu-i440fx/northbridge.c
@@ -52,6 +52,9 @@ static void cpu_pci_domain_set_resources(device_t dev)
 
 static void cpu_pci_domain_read_resources(struct device *dev)
 {
+	u16 nbid   = pci_read_config16(dev_find_slot(0, 0), PCI_DEVICE_ID);
+	int i440fx = (nbid == 0x1237);
+//	int q35    = (nbid == 0x29c0);
 	struct resource *res;
 	unsigned long tomk = 0, high;
 	int idx = 10;
@@ -89,14 +92,17 @@ static void cpu_pci_domain_read_resources(struct device *dev)
 	high_tables_size = HIGH_MEMORY_SIZE;
 #endif
 
-	/* Reserve space for the IOAPIC.  This should be in the Southbridge,
-	 * but I couldn't tell which device to put it in. */
-	res = new_resource(dev, 2);
-	res->base = IO_APIC_ADDR;
-	res->size = 0x100000UL;
-	res->limit = 0xffffffffUL;
-	res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |
-		     IORESOURCE_ASSIGNED;
+	if (i440fx) {
+		/* Reserve space for the IOAPIC.  This should be in
+		 * the Southbridge, but I couldn't tell which device
+		 * to put it in. */
+		res = new_resource(dev, 2);
+		res->base = IO_APIC_ADDR;
+		res->size = 0x100000UL;
+		res->limit = 0xffffffffUL;
+		res->flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+			IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+	}
 
 	/* Reserve space for the LAPIC.  There's one in every processor, but
 	 * the space only needs to be reserved once, so we do it here. */