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superio/aspeed/ast2400: Add AST2500 support 

The AST2500 is similar to the AST2400, but it also supports ESPI mode.
In ESPI mode the IRQ level must be 0 and UART3/UART4 aren't usable.

Change-Id: Iea45740427ad56656040e6342f5316ec9d38122f
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37641
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Patrick Rudolph 2019-12-10 14:53:00 +01:00 committed by Patrick Georgi
parent 021462bb26
commit a4e9395979
2 changed files with 45 additions and 1 deletions
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22
src/superio/aspeed/ast2400/chip.h Normal file
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@ -0,0 +1,22 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SUPERIO_ASPEED__AST2400_CHIP_H__
#define __SUPERIO_ASPEED__AST2400_CHIP_H__
struct superio_aspeed_ast2400_config {
/* On AST2500 only 1: ESPI, 0: LPC */
bool use_espi;
};
#endif /* __SUPERIO_ASPEED__AST2400_CHIP_H__ */

24
src/superio/aspeed/ast2400/superio.c
View File

@ -22,12 +22,23 @@
#include <superio/common/ssdt.h> #include <superio/common/ssdt.h>
#include <arch/acpi.h> #include <arch/acpi.h>
#include "ast2400.h" #include "ast2400.h"
#include "chip.h"
static void ast2400_init(struct device *dev) static void ast2400_init(struct device *dev)
{ {
struct superio_aspeed_ast2400_config *conf = dev->chip_info;
if (!dev->enabled) if (!dev->enabled)
return; return;
if (conf && conf->use_espi) {
pnp_enter_conf_mode(dev);
pnp_set_logical_device(dev);
/* In ESPI mode must write 0 to IRQ level on every LDN */
pnp_write_config(dev, 0x70, 0);
pnp_exit_conf_mode(dev);
}
switch (dev->path.pnp.device) { switch (dev->path.pnp.device) {
case AST2400_KBC: case AST2400_KBC:
pc_keyboard_init(NO_AUX_DEVICE); pc_keyboard_init(NO_AUX_DEVICE);
@ -94,11 +105,22 @@ static struct pnp_info pnp_dev_info[] = {
static void enable_dev(struct device *dev) static void enable_dev(struct device *dev)
{ {
struct superio_aspeed_ast2400_config *conf = dev->chip_info;
if (conf && conf->use_espi) {
/* UART3 and UART4 are not usable in ESPI mode */
for (size_t i = 0; i < ARRAY_SIZE(pnp_dev_info); i++) {
if ((pnp_dev_info[i].function == AST2400_SUART3) ||
(pnp_dev_info[i].function == AST2400_SUART4))
pnp_dev_info[i].function = PNP_SKIP_FUNCTION;
}
}
pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info); pnp_dev_info);
} }
struct chip_operations superio_aspeed_ast2400_ops = { struct chip_operations superio_aspeed_ast2400_ops = {
CHIP_NAME("ASpeed AST2400 Super I/O") CHIP_NAME("ASpeed AST2400/AST2500 Super I/O")
.enable_dev = enable_dev, .enable_dev = enable_dev,
}; };