White space and coding style fixes.
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736 Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/511 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
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@ -27,7 +27,6 @@ struct gliutable gliu0table[] = {
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{.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
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{.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
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{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
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{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
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{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_P2D_BMO_1, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
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{.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
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{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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@ -38,7 +37,6 @@ struct gliutable gliu1table[] = {
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{.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
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{.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
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{.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_BM_4,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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{.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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{.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
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{.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
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@ -357,7 +355,7 @@ static void GLPCIInit(void)
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wrmsr(msrnum, msr);
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wrmsr(msrnum, msr);
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/* this is done elsewhere already, but it does no harm to do it more than once */
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/* this is done elsewhere already, but it does no harm to do it more than once */
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/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
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/* write serialize memory hole to PCI. Need to unWS when something is shadowed regardless of cachablility. */
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msr.lo = 0x021212121; /* cache disabled and write serialized */
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msr.lo = 0x021212121; /* cache disabled and write serialized */
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msr.hi = 0x021212121; /* cache disabled and write serialized */
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msr.hi = 0x021212121; /* cache disabled and write serialized */
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@ -510,6 +508,7 @@ static void GeodeLinkPriority(void)
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static uint64_t getShadow(void)
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static uint64_t getShadow(void)
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{
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{
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msr_t msr;
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msr_t msr;
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msr = rdmsr(GLIU0_P2D_SC_0);
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msr = rdmsr(GLIU0_P2D_SC_0);
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return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
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return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
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}
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}
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