White space and coding style fixes.
Change-Id: I14f39b5666fc18e8183723ec78a40a849d337736 Signed-off-by: Nils Jacobs <njacobs8@adsltotaal.nl> Reviewed-on: http://review.coreboot.org/511 Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
This commit is contained in:
Nils Jacobs
Peter Stuge
parent
79cfe7e024
commit
a4f06f183b
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@ -27,25 +27,23 @@ struct gliutable gliu0table[] = {
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{.desc_name=GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
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{.desc_name=GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
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{.desc_name=GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_P2D_BMO_1, .desc_type= BMO_DMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU0_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
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{.desc_name=GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
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{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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};
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struct gliutable gliu1table[] = {
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{.desc_name=GLIU1_P2D_BM_0,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
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{.desc_name=GLIU1_P2D_BM_1,.desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) +0x0FFFE0}, /* 80000-9ffff to Mc */
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{.desc_name=GLIU1_P2D_SC_0,.desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name=GLIU1_P2D_R_0,.desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_BM_4,.desc_type= BM_DMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_BM_3,.desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_GLD_MSR_COH,.desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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{.desc_name=GLIU1_IOD_SC_0,.desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
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{.desc_name=GL_END,.desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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{.desc_name=GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
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{.desc_name=GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
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{.desc_name=GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
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{.desc_name=GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
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{.desc_name=GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
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{.desc_name=GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
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{.desc_name=GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
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};
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struct gliutable *gliutables[] = {gliu0table, gliu1table, 0};
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struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
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struct msrinit
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{
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@ -53,7 +51,7 @@ struct msrinit
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msr_t msr;
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};
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struct msrinit ClockGatingDefault [] = {
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struct msrinit ClockGatingDefault[] = {
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{GLIU0_GLD_MSR_PM, {.hi=0x00,.lo=0x0005}},
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/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
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{MC_GLD_MSR_PM, {.hi=0x00,.lo=0x0000}},
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@ -91,7 +89,7 @@ struct msrinit ClockGatingPerformance[] = {
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};
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/* SET GeodeLink PRIORITY */
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struct msrinit GeodeLinkPriorityTable [] = {
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struct msrinit GeodeLinkPriorityTable[] = {
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{CPU_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0220}}, /* CPU Priority. */
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{DF_GLD_MSR_MASTER_CONF, {.hi=0x00,.lo=0x0000}}, /* DF Priority. */
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{VG_GLD_MSR_CONFIG, {.hi=0x00,.lo=0x0720}}, /* VG Primary and Secondary Priority. */
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@ -145,7 +143,7 @@ static void SysmemInit(struct gliutable *gl)
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printk(BIOS_DEBUG, "%s: enable for %dm bytes\n", __func__, sizembytes);
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sizebytes = sizembytes << 20;
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sizebytes -= SMM_SIZE*1024 +1;
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sizebytes -= SMM_SIZE * 1024 + 1;
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if (havedmi)
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sizebytes -= DMM_SIZE * 1024 + 1;
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@ -216,10 +214,10 @@ static void DMMGL1Init(struct gliutable *gl)
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static void SMMGL0Init(struct gliutable *gl)
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{
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msr_t msr;
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int sizebytes = sizeram()<<20;
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int sizebytes = sizeram() << 20;
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long offset;
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sizebytes -= SMM_SIZE*1024;
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sizebytes -= SMM_SIZE * 1024;
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if (havedmi)
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sizebytes -= DMM_SIZE * 1024;
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@ -231,10 +229,10 @@ static void SMMGL0Init(struct gliutable *gl)
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offset >>= 12;
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msr.hi = offset << 8;
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msr.hi |= SMM_OFFSET>>24;
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msr.hi |= SMM_OFFSET >> 24;
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msr.lo = SMM_OFFSET << 8;
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msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
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msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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@ -251,7 +249,7 @@ static void SMMGL1Init(struct gliutable *gl)
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msr.hi &= 0xffffff00;
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msr.hi |= (SMM_OFFSET >> 24);
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msr.lo = SMM_OFFSET << 8;
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msr.lo |= ((~(SMM_SIZE*1024)+1)>>12)&0xfffff;
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msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
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wrmsr(gl->desc_name, msr); /* MSR - See table above */
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msr = rdmsr(gl->desc_name);
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@ -260,8 +258,8 @@ static void SMMGL1Init(struct gliutable *gl)
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static void GLIUInit(struct gliutable *gl)
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{
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while (gl->desc_type != GL_END){
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switch(gl->desc_type){
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while (gl->desc_type != GL_END) {
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switch (gl->desc_type) {
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default:
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/* For Unknown types: Write then read MSR */
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writeglmsr(gl);
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@ -277,15 +275,15 @@ static void GLIUInit(struct gliutable *gl)
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DMMGL0Init(gl);
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break;
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case BM_DMM : /* check for a DMM entry */
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case BM_DMM: /* check for a DMM entry */
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DMMGL1Init(gl);
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break;
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case BMO_SMM : /* check for a SMM entry */
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case BMO_SMM: /* check for a SMM entry */
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SMMGL0Init(gl);
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break;
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case BM_SMM : /* check for a SMM entry */
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case BM_SMM: /* check for a SMM entry */
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SMMGL1Init(gl);
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break;
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}
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@ -311,13 +309,13 @@ static void GLPCIInit(void)
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/* R0 - GLPCI settings for Conventional Memory space. */
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msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */
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msr.lo = 0; /* 0 */
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msr.lo |= GLPCI_RC_LOWER_EN_SET+ GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
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msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
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msrnum = GLPCI_RC0;
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wrmsr(msrnum, msr);
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/* R1 - GLPCI settings for SysMem space. */
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/* Get systop from GLIU0 SYSTOP Descriptor */
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for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
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for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
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if (gliu0table[i].desc_type == R_SYSMEM) {
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gl = &gliu0table[i];
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break;
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@ -350,14 +348,14 @@ static void GLPCIInit(void)
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}
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/* R2 - GLPCI settings for SMM space. */
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msr.hi = ((SMM_OFFSET+(SMM_SIZE*1024-1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
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msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
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msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
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msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
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msrnum = GLPCI_RC2;
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wrmsr(msrnum, msr);
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/* this is done elsewhere already, but it does no harm to do it more than once */
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/* write serialize memory hole to PCI. Need to to unWS when something is shadowed regardless of cachablility. */
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/* write serialize memory hole to PCI. Need to unWS when something is shadowed regardless of cachablility. */
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msr.lo = 0x021212121; /* cache disabled and write serialized */
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msr.hi = 0x021212121; /* cache disabled and write serialized */
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@ -389,7 +387,7 @@ static void GLPCIInit(void)
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/* Set WSREQ */
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msrnum = CPU_DM_CONFIG0;
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msr = rdmsr(msrnum);
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msr.hi &= ~ (7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
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msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode. */
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wrmsr(msrnum, msr);
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@ -408,25 +406,25 @@ static void GLPCIInit(void)
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msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
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msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
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msr.lo &= ~ (0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
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msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
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msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
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msr.lo &= ~ (0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
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msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
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msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
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msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
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msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
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msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
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msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
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msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
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msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
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msr.hi &= ~ (0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
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msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
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msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
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msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
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msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
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msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
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msr.hi &= ~ (0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
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msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
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msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
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wrmsr(msrnum, msr);
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@ -439,13 +437,13 @@ static void GLPCIInit(void)
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/* GLPCI_SPARE */
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msrnum = GLPCI_SPARE;
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msr = rdmsr(msrnum);
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msr.lo &= ~ 0x7;
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msr.lo &= ~0x7;
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msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
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wrmsr(msrnum, msr);
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}
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/* Enable Clock Gating. */
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static void ClockGatingInit (void)
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static void ClockGatingInit(void)
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{
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msr_t msr;
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struct msrinit *gating = ClockGatingDefault;
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@ -479,7 +477,7 @@ performance:
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
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gating->msrnum, msr.hi, msr.lo);
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wrmsr(gating->msrnum, msr); /* MSR - See the table above */
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gating +=1;
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gating += 1;
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}
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}
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@ -489,7 +487,7 @@ static void GeodeLinkPriority(void)
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struct msrinit *prio = GeodeLinkPriorityTable;
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int i;
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for(i = 0; prio->msrnum != 0xffffffff; i++) {
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for (i = 0; prio->msrnum != 0xffffffff; i++) {
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msr = rdmsr(prio->msrnum);
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx is 0x%08x:0x%08x\n", __func__, prio->msrnum, msr.hi, msr.lo);
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msr.hi |= prio->msr.hi;
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@ -498,7 +496,7 @@ static void GeodeLinkPriority(void)
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printk(BIOS_DEBUG, "%s: MSR 0x%08lx will be set to 0x%08x:0x%08x\n", __func__,
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prio->msrnum, msr.hi, msr.lo);
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wrmsr(prio->msrnum, msr); /* MSR - See the table above */
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prio +=1;
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prio += 1;
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}
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}
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@ -510,6 +508,7 @@ static void GeodeLinkPriority(void)
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static uint64_t getShadow(void)
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{
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msr_t msr;
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msr = rdmsr(GLIU0_P2D_SC_0);
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return ( ( (uint64_t) msr.hi ) << 32 ) | msr.lo;
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}
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@ -538,7 +537,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
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}
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/* load up C000 settings in eax. */
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for ( ; bit; bit--) {
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for (; bit; bit--) {
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msr.lo <<= 8;
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msr.lo |= 1; /* cache disable PCI/Shadow memory */
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if (shadowByte && (1 << bit))
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@ -558,7 +557,7 @@ static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
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}
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/* load up E000 settings in eax. */
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for ( ; bit; bit--) {
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for (; bit; bit--) {
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msr.lo <<= 8;
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msr.lo |= 1; /* cache disable PCI/Shadow memory */
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if (shadowByte && (1 << bit))
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@ -579,7 +578,7 @@ static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
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/* Set the Enable Register. */
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msr = rdmsr(GLPCI_REN);
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msr.lo &= 0xFFFF00FF;
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msr.lo |= ( (shadowLo & 0xFFFF0000) >> 8);
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msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);
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wrmsr(GLPCI_REN, msr);
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}
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@ -591,7 +590,7 @@ static void setShadow(uint64_t shadowSettings)
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{
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int i;
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msr_t msr;
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struct gliutable* pTable;
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struct gliutable *pTable;
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uint32_t shadowLo, shadowHi;
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shadowLo = (uint32_t) shadowSettings;
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@ -600,7 +599,7 @@ static void setShadow(uint64_t shadowSettings)
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setShadowRCONF(shadowHi, shadowLo);
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setShadowGLPCI(shadowHi, shadowLo);
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for(i = 0; gliutables[i]; i++) {
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for (i = 0; gliutables[i]; i++) {
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for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {
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if (pTable->desc_type == SC_SHADOW) {
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@ -646,7 +645,7 @@ static void RCONFInit(void)
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uint8_t SysMemCacheProp;
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/* Locate SYSMEM entry in GLIU0table */
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for(i = 0; gliu0table[i].desc_name != GL_END; i++) {
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for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
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if (gliu0table[i].desc_type == R_SYSMEM) {
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gl = &gliu0table[i];
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break;
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@ -724,7 +723,7 @@ void northbridge_init_early(void)
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int i;
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printk(BIOS_DEBUG, "Enter %s\n", __func__);
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for(i = 0; gliutables[i]; i++)
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for (i = 0; gliutables[i]; i++)
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GLIUInit(gliutables[i]);
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GeodeLinkPriority();
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