t210: implement MBIST workaround
MBIST has left some registers in non-suggested states. This CL restores CAR CE's, SLCG overrides & PLLD settings. BUG=None BRANCH=None TEST=tested on Smaug, still boot to kernel Change-Id: I1ddb19dd9fb6d8fb4d36e67eedeb847c6fd9f774 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 37a1c90c6deb351b2ae2caa03e5076553126744b Original-Change-Id: I613b4ef622d64305d436cb8379a5170b0fe1c9af Original-Signed-off-by: Yen Lin <yelin@nvidia.com> Original-Reviewed-on: https://chromium-review.googlesource.com/282417 Original-Reviewed-by: Tom Warren <twarren@nvidia.com> Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/11039 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Yen Lin
Patrick Georgi
parent
21ee13c3ca
commit
a501a8f27f
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@ -22,6 +22,7 @@
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#include <arch/stages.h>
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#include <bootblock_common.h>
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#include <console/console.h>
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#include <delay.h>
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#include <program_loading.h>
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#include <soc/addressmap.h>
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#include <soc/clock.h>
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@ -58,11 +59,113 @@ void __attribute__((weak)) bootblock_mainboard_early_init(void)
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/* Empty default implementation. */
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}
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/*
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* Define operations for the workaround:
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* OP_SET : [reg] = val;
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* OP_OR : [reg] |= val;
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* OP_AND : [reg] &= val;
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* OP_UDELAY : udelay(val);
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*/
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typedef enum {
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OP_SET,
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OP_OR,
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OP_AND,
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OP_UDELAY, /* use val field as usec delay */
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} WAR_OP;
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struct workaround_op {
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WAR_OP op;
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u32 reg;
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u32 val;
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};
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/*
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* An array defines the sequence to perform the workaround
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*/
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static struct workaround_op workaround_sequence[] = {
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{OP_OR, 0x60006410, (1 << 15)}, /* CLK_SOURCE_SOR1: */
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{OP_AND, 0x60006410, ~(1 << 14)}, /* CLK_SEL1=1, CLK_SEL0=0 */
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{OP_OR, 0x600060d0, 0x40800000}, /* PLLD_BASE */
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{OP_SET, 0x600062ac, 0x40}, /* clear APE reset */
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{OP_SET, 0x60006294, 0x40000}, /* clear VIC reset */
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{OP_SET, 0x60006304, 0x18000000}, /* clear HOST1X & DISP1 reset */
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{OP_UDELAY, 0, 2},
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{OP_OR, 0x702d10a0, 0x400}, /* I2S0: I2S_CTRL.MASTER=1 */
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{OP_AND, 0x702d1088, ~1}, /* I2S0: I2S_CG.SLCG_ENABLE=0 */
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{OP_OR, 0x702d11a0, 0x400}, /* I2S1: I2S_CTRL.MASTER=1 */
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{OP_AND, 0x702d1188, ~1}, /* I2S1: I2S_CG.SLCG_ENABLE=0 */
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{OP_OR, 0x702d12a0, 0x400}, /* I2S2: I2S_CTRL.MASTER=1 */
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{OP_AND, 0x702d1288, ~1}, /* I2S2: I2S_CG.SLCG_ENABLE=0 */
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{OP_OR, 0x702d13a0, 0x400}, /* I2S3: I2S_CTRL.MASTER=1 */
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{OP_AND, 0x702d1388, ~1}, /* I2S3: I2S_CG.SLCG_ENABLE=0 */
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{OP_OR, 0x702d14a0, 0x400}, /* I2S4: I2S_CTRL.MASTER=1 */
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{OP_AND, 0x702d1488, ~1}, /* I2S4: I2S_CG.SLCG_ENABLE=0 */
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{OP_OR, 0x54200cf8, 4}, /* DC_COM_DSC_TOP_CTL[DSC_SLCG_OVERRIDE]=1 */
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{OP_SET, 0x543400c8, 0xffffffff}, /* NV_PVIC_THI_SLCG_OVERRIDE_LOW_A = 0xFFFF_FFFF */
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{OP_UDELAY, 0, 2},
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{OP_SET, 0x600062a8, 0x40}, /* set APE reset */
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{OP_SET, 0x60006300, 0x18000000}, /* set HOST1X & DISP1 reset */
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{OP_SET, 0x60006290, 0x40000}, /* set VIC reset */
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{OP_SET, 0x60006014, 0x020000c1}, /* CLK_ENB_H */
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{OP_SET, 0x60006010, 0x80400130}, /* CLK_ENB_L */
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{OP_SET, 0x60006018, 0x01f00200}, /* CLK_ENB_U */
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{OP_SET, 0x60006360, 0x80400808}, /* CLK_ENB_V */
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{OP_SET, 0x60006364, 0x402000fc}, /* CLK_ENB_W */
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{OP_SET, 0x60006280, 0x23000780}, /* CLK_ENB_X */
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{OP_SET, 0x60006298, 0x00000340}, /* CLK_ENB_Y */
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{OP_SET, 0x600060f8, 0x00000000}, /* LVL2_CLK_GATE_OVRA */
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{OP_SET, 0x600060fc, 0x00000000}, /* LVL2_CLK_GATE_OVRB */
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{OP_SET, 0x600063a0, 0x00000000}, /* LVL2_CLK_GATE_OVRC */
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{OP_SET, 0x600063a4, 0x01000000}, /* LVL2_CLK_GATE_OVRD, QSPI_CLK_OVR_ON=1 */
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{OP_SET, 0x60006554, 0x00000000}, /* LVL2_CLK_GATE_OVRE */
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{OP_AND, 0x600060d0, 0x1f7fffff}, /* PLLD_BASE: 31,30,29,23 = 0 */
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{OP_AND, 0x60006410, 0xffff3fff}, /* CLK_SOURCE_SOR1 15,14 = 0 */
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{OP_AND, 0x60006148, ~(7 << 29)}, /* CLK_SOURCE_VI: */
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{OP_OR, 0x60006148, (4 << 29)}, /* SRC=PLLP_OUT0 (4) */
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{OP_AND, 0x60006180, ~(7 << 29)}, /* CLK_SOURCE_HOST1X: */
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{OP_OR, 0x60006180, (4 << 29)}, /* SRC=PLLP_OUT0 (4) */
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{OP_AND, 0x600066a0, ~(7 << 29)}, /* CLK_SOURCE_NVENC: */
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{OP_OR, 0x600066a0, (4 << 29)} /* SRC=PLLP_OUT0 (4) */
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};
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/*
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* This workaround is to restore CAR CE's, SLCG overrides & PLLD settings
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*/
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static void mbist_workaround(void)
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{
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int i;
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u32 val;
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struct workaround_op *wa_op;
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for (i = 0; i < ARRAY_SIZE(workaround_sequence); ++i) {
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wa_op = &workaround_sequence[i];
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switch (wa_op->op) {
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case OP_SET:
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val = wa_op->val;
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break;
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case OP_OR:
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val = read32((void *)wa_op->reg) | wa_op->val;
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break;
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case OP_AND:
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val = read32((void *)wa_op->reg) & wa_op->val;
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break;
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case OP_UDELAY:
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udelay(wa_op->val);
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/* fall thru */
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default:
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continue;
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}
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write32((void *)wa_op->reg, val);
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}
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}
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void main(void)
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{
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// enable JTAG at the earliest stage
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enable_jtag();
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mbist_workaround();
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clock_early_uart();
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/* Configure mselect clock. */
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@ -90,6 +193,7 @@ void main(void)
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pmc_print_rst_status();
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bootblock_mainboard_init();
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printk(BIOS_INFO, "T210 bootblock: Mainboard bootblock init done\n");
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