ktqm77: Support native raminit
Change-Id: Ic90d3aa714e5681c5021e2b05275d57dce428de0 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: https://review.coreboot.org/13664 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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@ -12,11 +12,13 @@ config BOARD_SPECIFIC_OPTIONS # dummy
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select HAVE_OPTION_TABLE
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select HAVE_ACPI_RESUME
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select ENABLE_VMX
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select HAVE_MRC
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config USE_NATIVE_RAMINIT
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bool
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default n
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if !USE_NATIVE_RAMINIT
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config BOARD_SPECIFIC_OPTIONS_MRC # dummy
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def_bool y
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select HAVE_MRC
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endif
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config MAINBOARD_DIR
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string
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@ -28,6 +28,7 @@
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#include <console/console.h>
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#include <northbridge/intel/sandybridge/sandybridge.h>
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#include <northbridge/intel/sandybridge/raminit.h>
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#include <northbridge/intel/sandybridge/raminit_native.h>
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#include <southbridge/intel/bd82x6x/pch.h>
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#include <arch/cpu.h>
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#include <cpu/x86/msr.h>
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@ -153,6 +154,29 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
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*pei_data = pei_data_template;
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}
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const struct southbridge_usb_port mainboard_usb_ports[] = {
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/* enabled power usb oc pin */
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{ 1, 0, 0 }, /* P0: lower left USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P1: upper left USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P2: lower right USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P3: upper right USB 3.0 (OC0) */
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{ 1, 0, 0 }, /* P4: lower USB 2.0 (OC0) */
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{ 1, 0, 0 }, /* P5: upper USB 2.0 (OC0) */
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{ 1, 0, 0 }, /* P6: front panel USB 2.0 (OC0) */
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{ 1, 0, 0 }, /* P7: front panel USB 2.0 (OC0) */
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{ 1, 0, 4 }, /* P8: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P9: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P10: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P11: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P12: internal USB 2.0 (OC4) */
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{ 1, 0, 4 }, /* P13: internal USB 2.0 (OC4) */
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};
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void mainboard_get_spd(spd_raw_data *spd) {
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read_spd(&spd[0], 0x50);
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read_spd(&spd[2], 0x52);
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}
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void mainboard_early_init(int s3resume)
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{
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/* Enable PEG10 (1x16) */
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