diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index 31f7ced273..887a520d9a 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -299,9 +299,8 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 		File: "southbridge/intel/bd82x6x/acpi/pch.asl",
 	})
 
-	sb := Create(ctx, "early_southbridge.c")
+	sb := Create(ctx, "romstage.c")
 	defer sb.Close()
-	AddROMStageFile("early_southbridge.c", "")
 	Add_gpl(sb)
 	sb.WriteString(`#include <stdint.h>
 #include <string.h>
diff --git a/util/autoport/main.go b/util/autoport/main.go
index 3071559a3d..ed56a55982 100644
--- a/util/autoport/main.go
+++ b/util/autoport/main.go
@@ -827,10 +827,6 @@ func main() {
 		fmt.Fprintf(bi, "FIXME: put %s\n", missing)
 	}
 
-	rs := Create(ctx, "romstage.c")
-	defer rs.Close()
-	rs.WriteString("/* dummy file */\n")
-
 	if ROMSizeKB == 0 {
 		KconfigBool["BOARD_ROMSIZE_KB_2048"] = true
 		KconfigComment["BOARD_ROMSIZE_KB_2048"] = "FIXME: correct this"