nb/intel/x4x: Use new fixed BAR accessors
Some cases break reproducibility if refactored, and are left as-is. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: I163995c0b107860449c2f36ad63e4e4ca52decb2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51878 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Nico Huber
parent
93aab51ec1
commit
a5146f3239
6 changed files with 483 additions and 499 deletions
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@ -167,7 +167,7 @@ static u8 test_dq_aligned(const struct sysinfo *s, const u8 channel)
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for (count = 0; count < WT_PATTERN_SIZE; count++) {
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for (count1 = 0; count1 < WT_PATTERN_SIZE; count1++) {
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if ((count1 % 16) == 0)
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MCHBAR32(0xf90) = 1;
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mchbar_write32(0xf90, 1);
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const u32 pattern = write_training_schedule[count1];
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write32((u32 *)address + 8 * count1, pattern);
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write32((u32 *)address + 8 * count1 + 4, pattern);
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@ -620,7 +620,7 @@ static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank,
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write32((u32 *)address + 4, 0x12341234);
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udelay(5);
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FOR_EACH_BYTELANE(lane) {
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u8 dq_high = (MCHBAR8(0x561 + 0x400 * channel
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u8 dq_high = (mchbar_read8(0x561 + 0x400 * channel
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+ (lane * 4)) >> 7) & 1;
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high_found[lane] += dq_high;
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}
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@ -639,7 +639,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
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FOR_EACH_BYTELANE(lane)
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dqsset(channel, lane, &dqs_setting[lane]);
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saved_24d = MCHBAR8(0x24d + 0x400 * channel);
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saved_24d = mchbar_read8(0x24d + 0x400 * channel);
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/* Loop 0: Find DQ sample low, by decreasing */
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while (bytelane_ok != 0xff) {
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@ -715,7 +715,7 @@ static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank)
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s->dqs_settings[channel][lane] = dqs_setting[lane];
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}
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MCHBAR8(0x24d + 0x400 * channel) = saved_24d;
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mchbar_write8(0x24d + 0x400 * channel, saved_24d);
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return CB_SUCCESS;
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}
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@ -762,11 +762,9 @@ void search_write_leveling(struct sysinfo *s)
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printk(BIOS_DEBUG, "\tCH%d\n", ch);
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config = chanconfig_lut[s->dimm_config[ch]];
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MCHBAR8(0x5d8 + 0x400 * ch) = MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e;
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MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) &
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~0x3fff) | 0x3fff;
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MCHBAR8(0x265 + 0x400 * ch) =
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MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
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mchbar_clrbits8(0x5d8 + 0x400 * ch, 0x0e);
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mchbar_clrsetbits16(0x5c4 + 0x400 * ch, 0x3fff, 0x3fff);
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mchbar_clrbits8(0x265 + 0x400 * ch, 0x1f);
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/* find the first populated rank */
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FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
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break;
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@ -776,41 +774,33 @@ void search_write_leveling(struct sysinfo *s)
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FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1)
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set_rank_write_level(s, ch, config, rank1, rank0, 1);
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MCHBAR8(0x298 + 2 + 0x400 * ch) =
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(MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f)
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| odt_force[config][rank0];
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MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) | 0x4e;
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MCHBAR8(0x5d9 + 0x400 * ch) = (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04;
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MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) | 0x00014000;
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mchbar_clrsetbits8(0x298 + 2 + 0x400 * ch, 0x0f, odt_force[config][rank0]);
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mchbar_clrsetbits8(0x271 + 0x400 * ch, 0x7e, 0x4e);
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mchbar_setbits8(0x5d9 + 0x400 * ch, 1 << 2);
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mchbar_clrsetbits32(0x1a0, 0x07ffffff, 0x00014000);
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if (increment_to_dqs_edge(s, ch, rank0))
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die("Write Leveling failed!");
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MCHBAR8(0x298 + 2 + 0x400 * ch) =
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MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f;
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MCHBAR8(0x271 + 0x400 * ch) =
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(MCHBAR8(0x271 + 0x400 * ch) & ~0x7e)
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| 0x0e;
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MCHBAR8(0x5d9 + 0x400 * ch) =
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(MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04);
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MCHBAR32(0x1a0) = (MCHBAR32(0x1a0)
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& ~0x07ffffff) | 0x00555801;
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mchbar_clrbits8(0x298 + 2 + 0x400 * ch, 0x0f);
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mchbar_clrsetbits8(0x271 + 0x400 * ch, 0x7e, 0x0e);
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mchbar_clrbits8(0x5d9 + 0x400 * ch, 1 << 2);
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mchbar_clrsetbits32(0x1a0, 0x07ffffff, 0x00555801);
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/* Disable WL on the trained rank */
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set_rank_write_level(s, ch, config, rank0, rank0, 0);
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send_jedec_cmd(s, rank0, ch, NORMALOP_CMD, 1 << 12);
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MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e;
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MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch)
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& ~0x3fff) | 0x1807;
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MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f;
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mchbar_setbits8(0x5d8 + 0x400 * ch, 0x0e);
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mchbar_clrsetbits16(0x5c4 + 0x400 * ch, 0x3fff, 0x1807);
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mchbar_clrbits8(0x265 + 0x400 * ch, 0x1f);
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/* Disable write level mode for all ranks */
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FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0)
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set_rank_write_level(s, ch, config, rank0, rank0, 0);
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}
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MCHBAR8(0x5dc) = (MCHBAR8(0x5dc) & ~0x80) | 0x80;
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mchbar_setbits8(0x5dc, 1 << 7);
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/* Increment DQ (rx) dll setting by a standard amount past DQS,
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This is further trained in write training. */
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@ -59,59 +59,59 @@ static void init_egress(void)
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u32 reg32;
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/* VC0: TC0 only */
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EPBAR8(EPVC0RCTL) = 1;
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EPBAR8(EPPVCCAP1) = 1;
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epbar_write8(EPVC0RCTL, 1);
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epbar_write8(EPPVCCAP1, 1);
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switch (MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
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switch (mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) {
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case 0x0:
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/* FSB 1066 */
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EPBAR32(EPVC1ITC) = 0x0001a6db;
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epbar_write32(EPVC1ITC, 0x0001a6db);
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break;
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case 0x2:
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/* FSB 800 */
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EPBAR32(EPVC1ITC) = 0x00014514;
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epbar_write32(EPVC1ITC, 0x00014514);
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break;
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default:
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case 0x4:
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/* FSB 1333 */
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EPBAR32(EPVC1ITC) = 0x00022861;
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epbar_write32(EPVC1ITC, 0x00022861);
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break;
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}
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EPBAR32(EPVC1MTS) = 0x0a0a0a0a;
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EPBAR8(EPPVCCTL) = (EPBAR8(EPPVCCTL) & ~0xe) | 2;
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EPBAR32(EPVC1RCAP) = (EPBAR32(EPVC1RCAP) & ~0x7f0000) | 0x0a0000;
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MCHBAR8(0x3c) = MCHBAR8(0x3c) | 0x7;
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epbar_write32(EPVC1MTS, 0x0a0a0a0a);
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epbar_clrsetbits8(EPPVCCTL, 7 << 1, 1 << 1);
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epbar_clrsetbits32(EPVC1RCAP, 0x7f << 16, 0x0a << 16);
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mchbar_setbits8(0x3c, 7);
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/* VC1: ID1, TC7 */
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reg32 = (EPBAR32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
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reg32 = (epbar_read32(EPVC1RCTL) & ~(7 << 24)) | (1 << 24);
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reg32 = (reg32 & ~0xfe) | (1 << 7);
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EPBAR32(EPVC1RCTL) = reg32;
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epbar_write32(EPVC1RCTL, reg32);
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/* Init VC1 port arbitration table */
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EPBAR32(EP_PORTARB(0)) = 0x001000001;
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EPBAR32(EP_PORTARB(1)) = 0x000040000;
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EPBAR32(EP_PORTARB(2)) = 0x000001000;
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EPBAR32(EP_PORTARB(3)) = 0x000000040;
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EPBAR32(EP_PORTARB(4)) = 0x001000001;
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EPBAR32(EP_PORTARB(5)) = 0x000040000;
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EPBAR32(EP_PORTARB(6)) = 0x000001000;
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EPBAR32(EP_PORTARB(7)) = 0x000000040;
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epbar_write32(EP_PORTARB(0), 0x001000001);
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epbar_write32(EP_PORTARB(1), 0x000040000);
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epbar_write32(EP_PORTARB(2), 0x000001000);
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epbar_write32(EP_PORTARB(3), 0x000000040);
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epbar_write32(EP_PORTARB(4), 0x001000001);
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epbar_write32(EP_PORTARB(5), 0x000040000);
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epbar_write32(EP_PORTARB(6), 0x000001000);
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epbar_write32(EP_PORTARB(7), 0x000000040);
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/* Load table */
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reg32 = EPBAR32(EPVC1RCTL) | (1 << 16);
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EPBAR32(EPVC1RCTL) = reg32;
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reg32 = epbar_read32(EPVC1RCTL) | (1 << 16);
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epbar_write32(EPVC1RCTL, reg32);
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asm("nop");
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EPBAR32(EPVC1RCTL) = reg32;
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epbar_write32(EPVC1RCTL, reg32);
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/* Wait for table load */
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while ((EPBAR8(EPVC1RSTS) & (1 << 0)) != 0)
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while ((epbar_read8(EPVC1RSTS) & (1 << 0)) != 0)
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;
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/* VC1: enable */
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EPBAR32(EPVC1RCTL) |= 1 << 31;
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epbar_setbits32(EPVC1RCTL, 1 << 31);
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/* Wait for VC1 */
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while ((EPBAR8(EPVC1RSTS) & (1 << 1)) != 0)
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while ((epbar_read8(EPVC1RSTS) & (1 << 1)) != 0)
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;
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printk(BIOS_DEBUG, "Done Egress Port\n");
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@ -124,22 +124,22 @@ static void init_dmi(void)
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/* Assume IGD present */
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/* Clear error status */
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DMIBAR32(DMIUESTS) = 0xffffffff;
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DMIBAR32(DMICESTS) = 0xffffffff;
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dmibar_write32(DMIUESTS, 0xffffffff);
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dmibar_write32(DMICESTS, 0xffffffff);
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/* VC0: TC0 only */
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DMIBAR8(DMIVC0RCTL) = 1;
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DMIBAR8(DMIPVCCAP1) = 1;
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dmibar_write8(DMIVC0RCTL, 1);
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dmibar_write8(DMIPVCCAP1, 1);
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/* VC1: ID1, TC7 */
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reg32 = (DMIBAR32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
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reg32 = (dmibar_read32(DMIVC1RCTL) & ~(7 << 24)) | (1 << 24);
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reg32 = (reg32 & ~0xff) | 1 << 7;
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/* VC1: enable */
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reg32 |= 1 << 31;
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reg32 = (reg32 & ~(0x7 << 17)) | (0x4 << 17);
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DMIBAR32(DMIVC1RCTL) = reg32;
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dmibar_write32(DMIVC1RCTL, reg32);
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/* Set up VCs in southbridge RCBA */
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RCBA8(0x3022) &= ~1;
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@ -202,17 +202,17 @@ static void init_dmi(void)
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/* Set up VC1 max time */
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RCBA32(0x1c) = (RCBA32(0x1c) & ~0x7f0000) | 0x120000;
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while ((DMIBAR32(DMIVC1RSTS) & VC1NP) != 0)
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while ((dmibar_read32(DMIVC1RSTS) & VC1NP) != 0)
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;
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printk(BIOS_DEBUG, "Done DMI setup\n");
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/* ASPM on DMI */
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DMIBAR32(0x200) &= ~(0x3 << 26);
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DMIBAR16(0x210) = (DMIBAR16(0x210) & ~(0xff7)) | 0x101;
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DMIBAR32(DMILCTL) &= ~0x3;
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DMIBAR32(DMILCTL) |= 0x3;
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dmibar_clrbits32(0x200, 3 << 26);
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dmibar_clrsetbits16(0x210, 0xff7, 0x101);
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dmibar_clrbits32(DMILCTL, 3);
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dmibar_setbits32(DMILCTL, 3);
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/* FIXME: Do we need to read RCBA16(DMILCTL)? Probably not. */
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DMIBAR16(DMILCTL);
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dmibar_read16(DMILCTL);
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}
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void x4x_late_init(void)
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@ -412,7 +412,7 @@ static void print_selected_timings(struct sysinfo *s)
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static void find_fsb_speed(struct sysinfo *s)
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{
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switch ((MCHBAR32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
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switch ((mchbar_read32(CLKCFG_MCHBAR) & CLKCFG_FSBCLK_MASK) >> CLKCFG_FSBCLK_SHIFT) {
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case 0x0:
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s->max_fsb = FSB_CLOCK_1066MHz;
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break;
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@ -532,7 +532,7 @@ static void checkreset_ddr2(int boot_path)
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u32 pmsts;
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if (boot_path >= 1) {
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pmsts = MCHBAR32(PMSTS_MCHBAR);
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pmsts = mchbar_read32(PMSTS_MCHBAR);
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if (!(pmsts & 1))
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printk(BIOS_DEBUG, "Channel 0 possibly not in self refresh\n");
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if (!(pmsts & 2))
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File diff suppressed because it is too large
Load diff
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@ -30,16 +30,16 @@ static u8 sampledqs(u32 addr, u8 lane, u8 channel)
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/* Reset the DQS probe, on both channels? */
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for (u8 i = 0; i < TOTAL_CHANNELS; i++) {
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MCHBAR8(RESET_CNTL(i)) &= ~0x2;
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mchbar_clrbits8(RESET_CNTL(i), 1 << 1);
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udelay(1);
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MCHBAR8(RESET_CNTL(i)) |= 0x2;
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mchbar_setbits8(RESET_CNTL(i), 1 << 1);
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udelay(1);
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}
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mfence();
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/* Read strobe */
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read32((u32 *)addr);
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mfence();
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return (MCHBAR8(sample_offset) >> 6) & 1;
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return mchbar_read8(sample_offset) >> 6 & 1;
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}
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static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
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@ -51,21 +51,21 @@ static void program_timing(const struct rec_timing *timing, u8 channel, u8 lane)
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printk(RAM_SPEW, " Programming timings:Coarse: %d, Medium: %d, TAP: %d, PI: %d\n",
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timing->coarse, timing->medium, timing->tap, timing->pi);
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reg32 = MCHBAR32(0x400 * channel + 0x248);
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reg32 = mchbar_read32(0x400 * channel + 0x248);
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reg32 &= ~0xf0000;
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reg32 |= timing->coarse << 16;
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MCHBAR32(0x400 * channel + 0x248) = reg32;
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mchbar_write32(0x400 * channel + 0x248, reg32);
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reg16 = MCHBAR16(0x400 * channel + 0x58c);
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reg16 = mchbar_read16(0x400 * channel + 0x58c);
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reg16 &= ~(3 << (lane * 2));
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reg16 |= timing->medium << (lane * 2);
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MCHBAR16(0x400 * channel + 0x58c) = reg16;
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mchbar_write16(0x400 * channel + 0x58c, reg16);
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reg8 = MCHBAR8(0x400 * channel + 0x560 + lane * 4);
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reg8 = mchbar_read8(0x400 * channel + 0x560 + lane * 4);
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reg8 &= ~0x7f;
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reg8 |= timing->tap;
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reg8 |= timing->pi << 4;
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MCHBAR8(0x400 * channel + 0x560 + lane * 4) = reg8;
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mchbar_write8(0x400 * channel + 0x560 + lane * 4, reg8);
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}
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static int increase_medium(struct rec_timing *timing)
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@ -241,8 +241,7 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
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{
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program_timing(timing, channel, lane);
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/* Set receive enable bit */
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MCHBAR16(0x400 * channel + 0x588) = (MCHBAR16(0x400 * channel + 0x588)
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& ~(3 << (lane * 2))) | (1 << (lane * 2));
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mchbar_clrsetbits16(0x400 * channel + 0x588, 3 << (lane * 2), 1 << (lane * 2));
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if (find_dqs_low(channel, lane, addr, timing))
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return -1;
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@ -275,8 +274,7 @@ static int calibrate_receive_enable(u8 channel, u8 lane,
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program_timing(timing, channel, lane);
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/* Unset receive enable bit */
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MCHBAR16(0x400 * channel + 0x588) = MCHBAR16(0x400 * channel + 0x588) &
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~(3 << (lane * 2));
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mchbar_clrbits16(0x400 * channel + 0x588, 3 << (lane * 2));
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return 0;
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}
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|
@ -294,9 +292,9 @@ void rcven(struct sysinfo *s)
|
|||
|
||||
printk(BIOS_DEBUG, "Starting DQS receiver enable calibration\n");
|
||||
|
||||
MCHBAR8(0x5d8) = MCHBAR8(0x5d8) & ~0xc;
|
||||
MCHBAR8(0x9d8) = MCHBAR8(0x9d8) & ~0xc;
|
||||
MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
|
||||
mchbar_clrbits8(0x5d8, 3 << 2);
|
||||
mchbar_clrbits8(0x9d8, 3 << 2);
|
||||
mchbar_clrbits8(0x5dc, 1 << 7);
|
||||
FOR_EACH_POPULATED_CHANNEL(s->dimms, channel) {
|
||||
mincoarse = 0xff;
|
||||
/*
|
||||
|
|
@ -355,9 +353,8 @@ void rcven(struct sysinfo *s)
|
|||
s->rcven_t[channel].medium[lane] = timing[lane].medium;
|
||||
s->rcven_t[channel].tap[lane] = timing[lane].tap;
|
||||
s->rcven_t[channel].pi[lane] = timing[lane].pi;
|
||||
MCHBAR16(0x400 * channel + 0x5fa) =
|
||||
(MCHBAR16(0x400 * channel + 0x5fa) &
|
||||
~(3 << (lane * 2))) | (reg8 << (lane * 2));
|
||||
mchbar_clrsetbits16(0x400 * channel + 0x5fa, 3 << (lane * 2),
|
||||
reg8 << (lane * 2));
|
||||
}
|
||||
/* simply use timing[0] to program mincoarse */
|
||||
timing[0].coarse = mincoarse;
|
||||
|
|
|
|||
|
|
@ -37,7 +37,7 @@ void mainboard_romstage_entry(void)
|
|||
|
||||
if (s3_resume)
|
||||
boot_path = BOOT_PATH_RESUME;
|
||||
if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
if (mchbar_read32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
|
||||
boot_path = BOOT_PATH_WARM_RESET;
|
||||
|
||||
mb_get_spd_map(spd_addr_map);
|
||||
|
|
|
|||
Loading…
Reference in a new issue