nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX IOMMU and the general IOMMU respectively. These addresses have to be configured in MCHBAR registers and reserved from the OS. GFXVTBAR/VTVC0BAR policy registers set to be consistent with proprietary vendor firmwares on hardware of same platform (2 different vendor firmwares compared, found to be identical). Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/24983 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier
Patrick Georgi
parent
8a6377ec24
commit
a51e379eaf
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@ -94,11 +94,39 @@ static void haswell_setup_graphics(void)
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MCHBAR32(0x5418) = reg32;
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}
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static void haswell_setup_iommu(void)
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{
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const u32 capid0_a = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A);
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if (capid0_a & VTD_DISABLE)
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return;
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/* setup BARs: zeroize top 32 bits; set enable bit */
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MCHBAR32(GFXVTBAR + 4) = GFXVT_BASE_ADDRESS >> 32;
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MCHBAR32(GFXVTBAR) = GFXVT_BASE_ADDRESS | 1;
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MCHBAR32(VTVC0BAR + 4) = VTVC0_BASE_ADDRESS >> 32;
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MCHBAR32(VTVC0BAR) = VTVC0_BASE_ADDRESS | 1;
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/* set L3HIT2PEND_DIS, lock GFXVTBAR policy cfg registers */
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u32 reg32;
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reg32 = read32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS));
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write32((void *)(GFXVT_BASE_ADDRESS + ARCHDIS),
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reg32 | DMAR_LCKDN | L3HIT2PEND_DIS);
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/* clear SPCAPCTRL */
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reg32 = read32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS)) & ~SPCAPCTRL;
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/* set GLBIOTLBINV, GLBCTXTINV; lock VTVC0BAR policy cfg registers */
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write32((void *)(VTVC0_BASE_ADDRESS + ARCHDIS),
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reg32 | DMAR_LCKDN | GLBIOTLBINV | GLBCTXTINV);
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}
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void haswell_early_initialization(int chipset_type)
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{
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/* Setup all BARs required for early PCIe and raminit */
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haswell_setup_bars();
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/* Setup IOMMU BARs */
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haswell_setup_iommu();
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/* Device Enable: IGD and Mini-HD Audio */
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pci_write_config32(PCI_DEV(0, 0, 0), DEVEN,
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DEVEN_D0EN | DEVEN_D2EN | DEVEN_D3EN);
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@ -35,6 +35,12 @@
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#endif
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#define DEFAULT_EPBAR 0xfed19000 /* 4 KB */
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#define GFXVT_BASE_ADDRESS 0xfed90000ULL
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#define GFXVT_BASE_SIZE 0x1000
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#define VTVC0_BASE_ADDRESS 0xfed91000ULL
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#define VTVC0_BASE_SIZE 0x1000
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#include <southbridge/intel/lynxpoint/pch.h>
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/* Everything below this line is ignored in the DSDT */
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@ -88,6 +94,16 @@
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#define SKPAD 0xdc /* Scratchpad Data */
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#define CAPID0_A 0xe4
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#define VTD_DISABLE (1 << 23)
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#define ARCHDIS 0xff0 /* DMA Remap Engine Policy Control */
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#define DMAR_LCKDN (1 << 31)
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#define SPCAPCTRL (1 << 25)
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#define L3HIT2PEND_DIS (1 << 20)
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#define PRSCAPDIS (1 << 2)
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#define GLBIOTLBINV (1 << 1)
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#define GLBCTXTINV (1 << 0)
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/* Device 0:1.0 PCI configuration space (PCI Express) */
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#define BCTRL1 0x3e /* 16bit */
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@ -107,6 +123,8 @@
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#define MCHBAR32_OR(x, or) MCHBAR32(x) = (MCHBAR32(x) | (or))
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#define BIOS_RESET_CPL 0x5da8 /* 8bit */
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#define GFXVTBAR 0x5400
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#define VTVC0BAR 0x5410
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/* Some power MSRs are also represented in MCHBAR */
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#define MCH_PKG_POWER_LIMIT_LO 0x59a0
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@ -290,7 +290,7 @@ static void mc_report_map_entries(device_t dev, uint64_t *values)
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printk(BIOS_DEBUG, "MC MAP: GGC: 0x%x\n", pci_read_config16(dev, GGC));
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}
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static void mc_add_dram_resources(device_t dev)
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static void mc_add_dram_resources(device_t dev, int *resource_cnt)
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{
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unsigned long base_k, size_k;
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unsigned long touud_k;
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@ -332,7 +332,7 @@ static void mc_add_dram_resources(device_t dev)
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* The resource index starts low and should not meet or exceed
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* PCI_BASE_ADDRESS_0.
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*/
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index = 0;
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index = *resource_cnt;
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/* 0 - > 0xa0000 */
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base_k = 0;
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@ -380,18 +380,31 @@ static void mc_add_dram_resources(device_t dev)
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CONFIG_CHROMEOS_RAMOOPS_RAM_START >> 10,
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CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10);
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#endif
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*resource_cnt = index;
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}
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static void mc_read_resources(device_t dev)
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{
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int index = 0;
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const bool vtd_capable =
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!(pci_read_config32(dev, CAPID0_A) & VTD_DISABLE);
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/* Read standard PCI resources. */
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pci_dev_read_resources(dev);
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/* Add all fixed MMIO resources. */
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mc_add_fixed_mmio_resources(dev);
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/* Add VT-d MMIO resources if capable */
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if (vtd_capable) {
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mmio_resource(dev, index++, GFXVT_BASE_ADDRESS / KiB,
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GFXVT_BASE_SIZE / KiB);
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mmio_resource(dev, index++, VTVC0_BASE_ADDRESS / KiB,
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VTVC0_BASE_SIZE / KiB);
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}
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/* Calculate and add DRAM resources. */
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mc_add_dram_resources(dev);
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mc_add_dram_resources(dev, &index);
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}
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static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device)
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@ -51,6 +51,10 @@ static void pch_enable_ioapic(struct device *dev)
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{
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u32 reg32;
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/* Assign unique bus/dev/fn for I/O APIC */
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pci_write_config16(dev, LPC_IBDF,
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PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
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/* Enable ACPI I/O range decode */
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pci_write_config8(dev, ACPI_CNTL, ACPI_EN);
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@ -396,9 +400,15 @@ static void lpt_lp_pm_init(struct device *dev)
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RCBA32_OR(0x33c8, (1 << 15));
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}
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static void enable_hpet(void)
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static void enable_hpet(struct device *const dev)
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{
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u32 reg32;
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size_t i;
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/* Assign unique bus/dev/fn for each HPET */
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for (i = 0; i < 8; ++i)
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pci_write_config16(dev, LPC_HnBDF(i),
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PCH_HPET_PCI_BUS << 8 | PCH_HPET_PCI_SLOT << 3 | i);
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/* Move HPET to default address 0xfed00000 and enable it */
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reg32 = RCBA32(HPTC);
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@ -570,7 +580,7 @@ static void lpc_init(struct device *dev)
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isa_dma_init();
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/* Initialize the High Precision Event Timers, if present. */
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enable_hpet();
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enable_hpet(dev);
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setup_i8259();
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@ -282,6 +282,8 @@ void pch_enable_lpc(void);
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#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
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#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
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#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */
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#define LPC_IBDF 0x6C /* I/O APIC bus/dev/fn */
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#define LPC_HnBDF(n) (0x70 + n * 2) /* HPET n bus/dev/fn */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
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@ -670,6 +672,11 @@ void pch_enable_lpc(void);
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#define PCH_DISABLE_MEI1 (1 << 1)
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#define PCH_ENABLE_DBDF (1 << 0)
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#define PCH_IOAPIC_PCI_BUS 250
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#define PCH_IOAPIC_PCI_SLOT 31
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#define PCH_HPET_PCI_BUS 250
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#define PCH_HPET_PCI_SLOT 15
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/* ICH7 PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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