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soc/intel: Move USB wake methods to a common ASL file 

The ACPI methods for enabling USB wake are identical on ADL, CNL and
SKL. Move them to a common ASL file so they can be reused more easily
on other SoCs.

Also move the USB_PORT_WAKE_ENABLE macro used to create enable bitmasks
in devicetree to a common header.

BUG=b:300844110
TEST=Use abuild to build kinox, puff, and fizz with and without this
change. Check the generated dsdt.aml is unchanged.

Change-Id: Iabdfe2bece7fafc284ddf04382f1bbcacc370cce
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
This commit is contained in:
Reka Norman 2023-09-22 15:26:54 +10:00 committed by Felix Held
parent 773d4b8fb0
commit a5215c4eb3
11 changed files with 65 additions and 156 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
src/soc/intel/alderlake/acpi/xhci.asl
View File

@ -3,51 +3,8 @@
#include <intelblocks/xhci.h>
#include <soc/gpe.h>
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UPWE, 3, Serialized)
{
Local0 = Arg1 + ((Arg0 - 1) * 0x10)
/* Map ((XMEM << 16) + Local0 in PSCR */
OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10)
Field (PSCR, DWordAcc, NoLock, Preserve)
{
PSCT, 32,
}
Local0 = PSCT
Local0 &= PORTSCN_BITS_OFF_MASK
Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}
/*
* USB Wake Enable Setup (UWES)
* Arg0 - Port enable bitmap
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UWES, 3, Serialized)
{
Local0 = Arg0
While (1) {
FindSetRightBit (Local0, Local1)
If (Local1 == 0) {
Break
}
UPWE (Local1, Arg1, Arg2)
/*
* Clear the lowest set bit in Local0 since it was
* processed.
*/
Local0 &= (Local0 - 1)
}
}
/* Include UWES method for enabling USB wake */
#include <soc/intel/common/acpi/xhci_wake.asl>
/* XHCI Controller 0:14.0 */

1
src/soc/intel/alderlake/chip.h
View File

@ -12,6 +12,7 @@
#include <intelblocks/power_limit.h>
#include <intelblocks/pcie_rp.h>
#include <intelblocks/tcss.h>
#include <intelblocks/xhci.h>
#include <soc/gpe.h>
#include <soc/pci_devs.h>
#include <soc/pmc.h>

7
src/soc/intel/alderlake/include/soc/usb.h
View File

@ -163,11 +163,4 @@ struct tcss_port_config {
.ocpin = (pin), \
}
/*
* Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
* to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
* decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
*/
#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1))
#endif

47
src/soc/intel/cannonlake/acpi/xhci.asl
View File

@ -3,51 +3,8 @@
#include <intelblocks/xhci.h>
#include <soc/gpe.h>
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UPWE, 3, Serialized)
{
Local0 = Arg1 + ((Arg0 - 1) * 0x10)
/* Map ((XMEM << 16) + Local0 in PSCR */
OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10)
Field (PSCR, DWordAcc, NoLock, Preserve)
{
PSCT, 32,
}
Local0 = PSCT
Local0 = Local0 & PORTSCN_BITS_OFF_MASK
Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}
/*
* USB Wake Enable Setup (UWES)
* Arg0 - Port enable bitmap
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UWES, 3, Serialized)
{
Local0 = Arg0
While (1) {
FindSetRightBit (Local0, Local1)
If (Local1 == 0) {
Break
}
UPWE (Local1, Arg1, Arg2)
/*
* Clear the lowest set bit in Local0 since it was
* processed.
*/
Local0 = Local0 & (Local0 - 1)
}
}
/* Include UWES method for enabling USB wake */
#include <soc/intel/common/acpi/xhci_wake.asl>
/* XHCI Controller 0:14.0 */

1
src/soc/intel/cannonlake/chip.h
View File

@ -10,6 +10,7 @@
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/xhci.h>
#include <stdbool.h>
#include <stdint.h>
#include <soc/pch.h>

7
src/soc/intel/cannonlake/include/soc/usb.h
View File

@ -186,11 +186,4 @@ struct usb3_port_config {
.gen2_rx_filter_sel = 0x44, \
}
/*
* Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
* to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
* decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
*/
#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1))
#endif

49
src/soc/intel/common/acpi/xhci_wake.asl Normal file
View File

@ -0,0 +1,49 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <intelblocks/xhci.h>
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UPWE, 3, Serialized)
{
Local0 = Arg1 + ((Arg0 - 1) * 0x10)
/* Map ((XMEM << 16) + Local0 in PSCR */
OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10)
Field (PSCR, DWordAcc, NoLock, Preserve)
{
PSCT, 32,
}
Local0 = PSCT
Local0 &= PORTSCN_BITS_OFF_MASK
Local0 |= PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}
/*
* USB Wake Enable Setup (UWES)
* Arg0 - Port enable bitmap
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UWES, 3, Serialized)
{
Local0 = Arg0
While (1) {
FindSetRightBit (Local0, Local1)
If (Local1 == 0) {
Break
}
UPWE (Local1, Arg1, Arg2)
/*
* Clear the lowest set bit in Local0 since it was
* processed.
*/
Local0 &= (Local0 - 1)
}
}

7
src/soc/intel/common/block/include/intelblocks/xhci.h
View File

@ -16,6 +16,13 @@
#define PORTSCN_BITS_OFF_MASK ~0x80FE0012
#define PORTSCXUSB3_OFFSET 0x540
/*
* Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
* to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
* decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
*/
#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1))
#if !defined(__ACPI__)
#include <device/device.h>
#include <device/xhci.h>

47
src/soc/intel/skylake/acpi/xhci.asl
View File

@ -2,51 +2,8 @@
#include <intelblocks/xhci.h>
/*
* USB Port Wake Enable (UPWE) on usb attach/detach
* Arg0 - Port Number
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UPWE, 3, Serialized)
{
Local0 = Arg1 + ((Arg0 - 1) * 0x10)
/* Map ((XMEM << 16) + Local0 in PSCR */
OperationRegion (PSCR, SystemMemory, (Arg2 << 16) + Local0, 0x10)
Field (PSCR, DWordAcc, NoLock, Preserve)
{
PSCT, 32,
}
Local0 = PSCT
Local0 = Local0 & PORTSCN_BITS_OFF_MASK
Local0 = Local0 | PORTSCN_WAKE_ON_BOTH_CONNECT_DISCONNECT_ENABLE
PSCT = Local0
}
/*
* USB Wake Enable Setup (UWES)
* Arg0 - Port enable bitmap
* Arg1 - Port 1 Status and control offset
* Arg2 - xHCI Memory-mapped address
*/
Method (UWES, 3, Serialized)
{
Local0 = Arg0
While (1) {
FindSetRightBit (Local0, Local1)
If (Local1 == 0) {
Break
}
UPWE (Local1, Arg1, Arg2)
/*
* Clear the lowest set bit in Local0 since it was
* processed.
*/
Local0 = Local0 & (Local0 - 1)
}
}
/* Include UWES method for enabling USB wake */
#include <soc/intel/common/acpi/xhci_wake.asl>
/* XHCI Controller 0:14.0 */

1
src/soc/intel/skylake/chip.h
View File

@ -12,6 +12,7 @@
#include <intelblocks/gspi.h>
#include <intelblocks/lpc_lib.h>
#include <intelblocks/power_limit.h>
#include <intelblocks/xhci.h>
#include <stdbool.h>
#include <stdint.h>
#include <soc/gpe.h>

7
src/soc/intel/skylake/include/soc/usb.h
View File

@ -180,11 +180,4 @@ struct usb3_port_config {
.tx_downscale_amp = 0x00, \
}
/*
* Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds
* to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to
* decide what ports need to set PORTSCN/PORTSCXUSB3 register bits.
*/
#define USB_PORT_WAKE_ENABLE(x) (1 << ((x) - 1))
#endif