soc/intel/quark: Split I2C out from driver
Split out the I2C code to allow I2C transactions during early romstage. TEST=Build and run on Galileo Gen2 Change-Id: I87ceb0a8cf660e4337738b3bcde9d4fdeae0159d Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15007 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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@ -18,6 +18,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y)
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subdirs-y += romstage
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subdirs-y += ../../../cpu/x86/tsc
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romstage-y += i2c.c
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romstage-y += memmap.c
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romstage-y += reg_access.c
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romstage-y += tsc_freq.c
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@ -27,6 +28,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
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ramstage-y += chip.c
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ramstage-y += ehci.c
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ramstage-y += gpio_i2c.c
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ramstage-y += i2c.c
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ramstage-y += lpc.c
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ramstage-y += memmap.c
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ramstage-y += northcluster.c
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@ -23,158 +23,6 @@
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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static void i2c_disable(I2C_REGS *regs)
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{
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uint32_t status;
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uint32_t timeout;
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/* Disable I2C controller */
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regs->ic_enable = 0;
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/* Wait for the enable bit to clear */
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timeout = 1 * 1000 * 1000;
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status = regs->ic_enable_status;
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while (status & IC_ENABLE_CONTROLLER) {
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udelay(1);
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if (--timeout == 0)
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die("ERROR - I2C failed to disable!\n");
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status = regs->ic_enable_status;
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}
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/* Clear any pending interrupts */
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status = regs->ic_clr_intr;
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}
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int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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{
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uint8_t *buffer;
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int bytes_transferred;
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uint8_t chip;
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uint32_t cmd;
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int length;
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int read_length;
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I2C_REGS *regs;
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uint32_t status;
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uint32_t timeout;
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regs = get_i2c_address();
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/* Disable the I2C controller to get access to the registers */
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i2c_disable(regs);
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/* Set the slave address */
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ASSERT (count > 0);
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ASSERT (segments != NULL);
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ASSERT (segments->read == 0);
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/* Clear the start and stop detection */
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status = regs->ic_clr_start_det;
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status = regs->ic_clr_stop_det;
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/* Set addressing mode to 7-bit and fast mode */
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cmd = regs->ic_con;
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cmd &= ~(IC_CON_10B | IC_CON_SPEED);
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cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz
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| IC_CON_MASTER_MODE;
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regs->ic_con = cmd;
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/* Set the target chip address */
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chip = segments->chip;
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regs->ic_tar = chip;
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/* Enable the I2C controller */
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regs->ic_enable = IC_ENABLE_CONTROLLER;
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/* Clear the interrupts */
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status = regs->ic_clr_rx_under;
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status = regs->ic_clr_rx_over;
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status = regs->ic_clr_tx_over;
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status = regs->ic_clr_tx_abrt;
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/* Process each of the segments */
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bytes_transferred = 0;
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read_length = 0;
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buffer = NULL;
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while (count-- > 0) {
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buffer = segments->buf;
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length = segments->len;
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ASSERT (buffer != NULL);
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ASSERT (length >= 1);
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ASSERT (segments->chip = chip);
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if (segments->read) {
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/* Place read commands into the FIFO */
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read_length = length;
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while (length > 0) {
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/* Send stop bit after last byte */
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cmd = IC_DATA_CMD_READ;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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/* Place read command in transmit FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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}
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} else {
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/* Write the data into the FIFO */
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while (length > 0) {
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/* End of the transaction? */
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cmd = IC_DATA_CMD_WRITE | *buffer++;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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/* Place a data byte into the FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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bytes_transferred++;
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}
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}
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segments++;
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}
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/* Wait for the end of the transaction */
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timeout = 1 * 1000 * 1000;
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do {
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status = regs->ic_raw_intr_stat;
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if (status & IC_INTR_STOP_DET)
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break;
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if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER))
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|| (timeout == 0)) {
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if (timeout == 0)
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printk (BIOS_ERR,
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"ERROR - I2C stop bit not received!\n");
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if (status & IC_INTR_RX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C receive overrun!\n");
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if (status & IC_INTR_RX_UNDER)
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printk (BIOS_ERR,
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"ERROR - I2C receive underrun!\n");
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if (status & IC_INTR_TX_ABRT)
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printk (BIOS_ERR,
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"ERROR - I2C transmit abort!\n");
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if (status & IC_INTR_TX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C transmit overrun!\n");
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i2c_disable(regs);
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return -1;
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}
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timeout--;
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udelay(1);
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} while(1);
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/* Finish reading the data bytes */
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while (read_length > 0) {
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status = regs->ic_status;
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*buffer++ = (UINT8)regs->ic_data_cmd;
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read_length--;
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bytes_transferred++;
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status = regs->ic_status;
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}
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return bytes_transferred;
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}
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__attribute__((weak)) void mainboard_gpio_i2c_init(device_t dev)
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{
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/* Initialize any of the GPIOs or I2C devices */
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@ -0,0 +1,176 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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#include <device/i2c.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <soc/i2c.h>
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#include <soc/ramstage.h>
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#include <soc/reg_access.h>
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static void i2c_disable(I2C_REGS *regs)
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{
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uint32_t status;
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uint32_t timeout;
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/* Disable I2C controller */
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regs->ic_enable = 0;
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/* Wait for the enable bit to clear */
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timeout = 1 * 1000 * 1000;
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status = regs->ic_enable_status;
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while (status & IC_ENABLE_CONTROLLER) {
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udelay(1);
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if (--timeout == 0)
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die("ERROR - I2C failed to disable!\n");
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status = regs->ic_enable_status;
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}
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/* Clear any pending interrupts */
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status = regs->ic_clr_intr;
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}
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int platform_i2c_transfer(unsigned bus, struct i2c_seg *segments, int count)
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{
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uint8_t *buffer;
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int bytes_transferred;
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uint8_t chip;
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uint32_t cmd;
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int length;
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int read_length;
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I2C_REGS *regs;
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uint32_t status;
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uint32_t timeout;
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regs = get_i2c_address();
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/* Disable the I2C controller to get access to the registers */
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i2c_disable(regs);
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/* Set the slave address */
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ASSERT (count > 0);
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ASSERT (segments != NULL);
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ASSERT (segments->read == 0);
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/* Clear the start and stop detection */
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status = regs->ic_clr_start_det;
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status = regs->ic_clr_stop_det;
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/* Set addressing mode to 7-bit and fast mode */
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cmd = regs->ic_con;
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cmd &= ~(IC_CON_10B | IC_CON_SPEED);
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cmd |= IC_CON_RESTART_EN | IC_CON_7B | IC_CON_SPEED_100_KHz
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| IC_CON_MASTER_MODE;
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regs->ic_con = cmd;
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/* Set the target chip address */
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chip = segments->chip;
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regs->ic_tar = chip;
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/* Enable the I2C controller */
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regs->ic_enable = IC_ENABLE_CONTROLLER;
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/* Clear the interrupts */
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status = regs->ic_clr_rx_under;
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status = regs->ic_clr_rx_over;
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status = regs->ic_clr_tx_over;
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status = regs->ic_clr_tx_abrt;
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/* Process each of the segments */
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bytes_transferred = 0;
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read_length = 0;
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buffer = NULL;
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while (count-- > 0) {
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buffer = segments->buf;
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length = segments->len;
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ASSERT (buffer != NULL);
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ASSERT (length >= 1);
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ASSERT (segments->chip = chip);
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if (segments->read) {
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/* Place read commands into the FIFO */
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read_length = length;
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while (length > 0) {
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/* Send stop bit after last byte */
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cmd = IC_DATA_CMD_READ;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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/* Place read command in transmit FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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}
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} else {
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/* Write the data into the FIFO */
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while (length > 0) {
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/* End of the transaction? */
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cmd = IC_DATA_CMD_WRITE | *buffer++;
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if ((count == 0) && (length == 1))
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cmd |= IC_DATA_CMD_STOP;
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/* Place a data byte into the FIFO */
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regs->ic_data_cmd = cmd;
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length--;
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bytes_transferred++;
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}
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}
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segments++;
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}
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/* Wait for the end of the transaction */
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timeout = 1 * 1000 * 1000;
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do {
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status = regs->ic_raw_intr_stat;
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if (status & IC_INTR_STOP_DET)
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break;
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if ((status & (IC_INTR_RX_OVER | IC_INTR_RX_UNDER
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| IC_INTR_TX_ABRT | IC_INTR_TX_OVER))
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|| (timeout == 0)) {
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if (timeout == 0)
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printk (BIOS_ERR,
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"ERROR - I2C stop bit not received!\n");
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if (status & IC_INTR_RX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C receive overrun!\n");
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if (status & IC_INTR_RX_UNDER)
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printk (BIOS_ERR,
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"ERROR - I2C receive underrun!\n");
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if (status & IC_INTR_TX_ABRT)
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printk (BIOS_ERR,
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"ERROR - I2C transmit abort!\n");
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if (status & IC_INTR_TX_OVER)
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printk (BIOS_ERR,
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"ERROR - I2C transmit overrun!\n");
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i2c_disable(regs);
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return -1;
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}
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timeout--;
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udelay(1);
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} while(1);
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/* Finish reading the data bytes */
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while (read_length > 0) {
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status = regs->ic_status;
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*buffer++ = (UINT8)regs->ic_data_cmd;
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read_length--;
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bytes_transferred++;
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status = regs->ic_status;
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}
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return bytes_transferred;
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}
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