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mb/siemens/mc_apl2: Set Full Reset Bit into Reset Control Register 

With the introduction of a new Linux version a problem has appeared
after a software initiated reset via CF9h register. The problem
manifests itself in the fact that the Linux kernel does not start after
the reboot. The problem is solved by setting bit 3 to 1 in Reset Control
Register (I/O port CF9h). This leads to the fact that the PCH will drive
SLP_S3 active low in the reset sequence. It leads to the same behavior
as in commit 04ea73ee78 ("siemens/mc_apl3: Set Full Reset Bit into
Reset Control Register") explained.

Change-Id: Ibc6d538c939e38732f42995d5ec6c8b61f979a6a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77603
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Mario Scheithauer 2023-09-01 07:54:20 +02:00 committed by Martin L Roth
parent fd6908a748
commit a52d38b637
1 changed files with 6 additions and 0 deletions
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6
src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c
View File

@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <cf9_reset.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
@ -17,4 +18,9 @@ void variant_mainboard_final(void)
pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
}
}
/* Set Full Reset Bit in Reset Control Register (I/O port CF9h). When Bit 3 is set to 1
and then a warm reset is triggered the PCH will drive SLP_S3 active (low). SLP_S3 is
then used on the mainboard to generate the right reset timing. */
outb(FULL_RST, RST_CNT);
}