mb/asrock/h110m: fix VR domains configuration
1) VR domains current limit Icc max for Sky/Kaby Lake S is set based on the processor TDP [1]. Updates information about this 2) Sets VR voltage limit to 1.52V, as described in the datasheets [2,3] [1] Change-Id: I303c5dc8ed03e9a98a834a2acfb400022dfc2fde [2] page 112-119, 6th Generation Intel(R) Processor Families for S-Platforms, Volume 1 of 2, Datasheet, August 2018. Document Number: 332687-008EN [3] 7th Generation Intel(R) Processor Families for S Platforms and Intel(R) Core(TM) X-Series Processor Family Datasheet, Volume 1, December 2018, Document Number: 335195-003 Change-Id: I6e1aefde135ffce75a5d837348595aa20aff0513 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -89,9 +89,10 @@ chip soc/intel/skylake
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| IccMax* | 0 | 0 | 0 | 0 | 0 |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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# * - is set automatically for the KBL-S/KBL-DT CPUs in the vr_config.c
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1, \
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.psi1threshold = 0x50, \
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@ -102,7 +103,7 @@ chip soc/intel/skylake
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 0x0 \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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@ -115,7 +116,7 @@ chip soc/intel/skylake
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 0x0 \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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@ -128,7 +129,7 @@ chip soc/intel/skylake
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0 ,\
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.voltage_limit = 0x0 \
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.voltage_limit = 1520 \
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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@ -141,7 +142,7 @@ chip soc/intel/skylake
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.imon_slope = 0x0, \
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.imon_offset = 0x0, \
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.icc_max = 0x0, \
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.voltage_limit = 0x0 \
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.voltage_limit = 1520 \
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}"
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register "EnableLan" = "0"
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