purism/librem_skl: add new variant Librem 15 v3
Add new board librem15v3 as a variant of the librem_skl baseboard. Changes from the librem13v2: - Change board name and version - Change GPIO A18, A19, A20, D9, D10 and D11 from NC to GPIO - Enable PCI device 1c.4 - Change USB port definitions in devicetree TEST: build w/SeaBIOS, boot PureOS on Librem 15 v3 hardware Change-Id: I7c762a34f5b961c908e4a29ec331da4b0dea9986 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/22048 Reviewed-by: Youness Alaoui <snifikino@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Matt DeVillier
parent
c6202e8c00
commit
a547e40992
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@ -18,6 +18,7 @@ config IRQ_SLOT_COUNT
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config VARIANT_DIR
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string
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default "librem13v2" if BOARD_PURISM_LIBREM13_V2
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default "librem15v3" if BOARD_PURISM_LIBREM15_V3
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config MAINBOARD_VENDOR
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string
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@ -26,14 +27,17 @@ config MAINBOARD_VENDOR
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config MAINBOARD_FAMILY
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string
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default "Librem 13" if BOARD_PURISM_LIBREM13_V2
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default "Librem 15" if BOARD_PURISM_LIBREM15_V3
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config MAINBOARD_PART_NUMBER
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string
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default "Librem 13 v2" if BOARD_PURISM_LIBREM13_V2
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default "Librem 15 v3" if BOARD_PURISM_LIBREM15_V3
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config MAINBOARD_VERSION
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string
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default "2.0" if BOARD_PURISM_LIBREM13_V2
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default "3.0" if BOARD_PURISM_LIBREM15_V3
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config MAINBOARD_DIR
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string
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@ -42,6 +46,7 @@ config MAINBOARD_DIR
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config DEVICETREE
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string
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default "variants/librem13v2/devicetree.cb" if BOARD_PURISM_LIBREM13_V2
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default "variants/librem15v3/devicetree.cb" if BOARD_PURISM_LIBREM15_V3
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config MAX_CPUS
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int
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@ -1,3 +1,7 @@
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config BOARD_PURISM_LIBREM13_V2
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bool "Librem 13 v2"
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select BOARD_PURISM_BASEBOARD_LIBREM_SKL
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config BOARD_PURISM_LIBREM15_V3
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bool "Librem 15 v3"
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select BOARD_PURISM_BASEBOARD_LIBREM_SKL
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@ -0,0 +1,9 @@
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Vendor name: Purism
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Board name: Librem 15 v3
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Board URL: https://puri.sm/librem-15/
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Category: laptop
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2017
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@ -0,0 +1,213 @@
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "0"
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register "deep_s5_enable_dc" = "0"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "1"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[1]" = "0"
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register "SataPortsEnable[2]" = "1"
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register "SataPortsDevSlp[0]" = "0"
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register "SataPortsDevSlp[2]" = "0"
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register "SataSpeedLimit" = "2"
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register "EnableAzalia" = "1"
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register "DspEnable" = "0"
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register "IoBufferOwnership" = "0"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "0"
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register "ScsEmmcHs400Enabled" = "0"
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register "ScsSdCardEnabled" = "0"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "FspSkipMpInit" = "1"
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register "SaGv" = "3"
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register "SerialIrqConfigSirqEnable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "3" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "0"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 4 Domains
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#+----------------+-------+-------+-------------+-------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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# Enable Root Ports 5 and 9
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register "PcieRpEnable[4]" = "1"
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register "PcieRpEnable[8]" = "1"
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# Enable CLKREQ# for RP9
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register "PcieRpClkReqSupport[8]" = "0"
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# ClkReq for NVMe - Bruteforced (no other value works)
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register "PcieRpClkReqNumber[8]" = "2"
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register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
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register "usb2_ports[1]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
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register "usb2_ports[2]" = "USB2_PORT_MID(OC1)" # Type-A Port (right)
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register "usb2_ports[3]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
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register "usb2_ports[4]" = "USB2_PORT_FLEX(OC2)" # Type-A Port (left)
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register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
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register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
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register "usb2_ports[7]" = "USB2_PORT_FLEX(OC_SKIP)" # SD
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# OC0 should be for Type-C but it seems to not have been wired, according to
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# the available schematics, even though it is labeled as USB_OC_TYPEC.
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port (right)
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port
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# PL2 override 25W
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register "tdp_pl2_override" = "25"
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Lock Down
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register "chipset_lockdown" = "CHIPSET_LOCKDOWN_COREBOOT"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 02.0 on end # Integrated Graphics Device
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device pci 14.0 on end # USB xHCI
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device pci 14.1 on end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 1c.0 on end # PCI Express Port 1
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device pci 1c.1 off end # PCI Express Port 2
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device pci 1c.2 off end # PCI Express Port 3
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device pci 1c.3 off end # PCI Express Port 4
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device pci 1c.4 on end # PCI Express Port 5
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device pci 1c.5 off end # PCI Express Port 6
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device pci 1c.6 off end # PCI Express Port 7
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device pci 1c.7 off end # PCI Express Port 8
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device pci 1d.0 on end # PCI Express Port 9
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device pci 1d.1 off end # PCI Express Port 10
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device pci 1d.2 off end # PCI Express Port 11
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device pci 1d.3 off end # PCI Express Port 12
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device pci 1f.0 on
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chip ec/purism/librem
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device pnp 0c09.0 on end
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end
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end # LPC Interface
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 on end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # PCH SPI
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device pci 1f.6 off end # GbE
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end
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end
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@ -0,0 +1,201 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*/
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#ifndef MAINBOARD_GPIO_H
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#define MAINBOARD_GPIO_H
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#include <soc/gpe.h>
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#include <soc/gpio.h>
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#ifndef __ACPI__
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/* Pad configuration in ramstage. */
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static const struct pad_config gpio_table[] = {
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/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
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/* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
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/* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
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/* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
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/* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
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/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
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/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
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/* PIRQA# */ PAD_CFG_NC(GPP_A7),
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/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
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/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
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/* CLKOUT_LPC1 */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1),
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/* PME# */ PAD_CFG_NC(GPP_A11),
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/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
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/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
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/* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
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/* SUSACK# */ PAD_CFG_NF(GPP_A15, DN_20K, DEEP, NF1),
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/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
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/* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
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/* ISH_GP0 */ PAD_CFG_GPI(GPP_A18, NONE, DEEP),
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/* ISH_GP1 */ PAD_CFG_GPI(GPP_A19, NONE, DEEP),
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/* ISH_GP2 */ PAD_CFG_GPI(GPP_A20, NONE, DEEP),
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/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
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/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
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/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
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/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
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/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
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/* VRALERT# */ PAD_CFG_NC(GPP_B2),
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/* CPU_GP2 */ PAD_CFG_NC(GPP_B3),
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/* CPU_GP3 */ PAD_CFG_NC(GPP_B4),
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/* SRCCLKREQ0# */ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
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/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
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/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
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/* SRCCLKREQ3# */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
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/* SRCCLKREQ4# */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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/* SRCCLKREQ5# */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
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/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
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/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
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/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
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/* SPKR */ PAD_CFG_TERM_GPO(GPP_B14, 1, DN_20K, DEEP),
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/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
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/* GSPI0_CLK */ PAD_CFG_NC(GPP_B16),
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/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
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/* GSPI0_MOSI */ PAD_CFG_GPI_SCI(GPP_B18, UP_20K, PLTRST, LEVEL, INVERT),
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/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
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/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
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/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
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/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, DN_20K, DEEP, NF1),
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/* SM1ALERT# */ PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP),
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/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
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/* SMBDATA */ PAD_CFG_NF(GPP_C1, DN_20K, DEEP, NF1),
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/* SMBALERT# */ PAD_CFG_TERM_GPO(GPP_C2, 1, DN_20K, DEEP),
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/* SML0CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
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/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
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/* SML0ALERT# */ PAD_CFG_GPI_APIC_INVERT(GPP_C5, DN_20K, DEEP),
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/* SML1CLK */ PAD_CFG_NC(GPP_C6), /* RESERVED */
|
||||
/* SML1DATA */ PAD_CFG_NC(GPP_C7), /* RESERVED */
|
||||
/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
|
||||
/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
|
||||
/* UART0_RTS# */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1),
|
||||
/* UART0_CTS# */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1),
|
||||
/* UART1_RXD */ PAD_CFG_NC(GPP_C12),
|
||||
/* UART1_TXD */ PAD_CFG_NC(GPP_C13),
|
||||
/* UART1_RTS# */ PAD_CFG_NC(GPP_C14),
|
||||
/* UART1_CTS# */ PAD_CFG_NC(GPP_C15),
|
||||
/* I2C0_SDA */ PAD_CFG_GPI(GPP_C16, NONE, DEEP),
|
||||
/* I2C0_SCL */ PAD_CFG_GPI(GPP_C17, NONE, DEEP),
|
||||
/* I2C1_SDA */ PAD_CFG_GPI(GPP_C18, NONE, DEEP),
|
||||
/* I2C1_SCL */ PAD_CFG_NC(GPP_C19),
|
||||
/* UART2_RXD */ PAD_CFG_NC(GPP_C20),
|
||||
/* UART2_TXD */ PAD_CFG_NC(GPP_C21),
|
||||
/* UART2_RTS# */ PAD_CFG_NC(GPP_C22),
|
||||
/* UART2_CTS# */ PAD_CFG_NC(GPP_C23),
|
||||
|
||||
/* SPI1_CS# */ PAD_CFG_NC(GPP_D0),
|
||||
/* SPI1_CLK */ PAD_CFG_NC(GPP_D1),
|
||||
/* SPI1_MISO */ PAD_CFG_NC(GPP_D2),
|
||||
/* SPI1_MOSI */ PAD_CFG_NC(GPP_D3),
|
||||
/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
|
||||
/* ISH_I2C0_SDA */ PAD_CFG_NC(GPP_D5),
|
||||
/* ISH_I2C0_SCL */ PAD_CFG_NC(GPP_D6),
|
||||
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
|
||||
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
|
||||
/* ISH_SPI_CS# */ PAD_CFG_TERM_GPO(GPP_D9, 0, NONE, DEEP),
|
||||
/* ISH_SPI_CLK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP),
|
||||
/* ISH_SPI_MISO */ PAD_CFG_TERM_GPO(GPP_D11, 1, NONE, DEEP),
|
||||
/* ISH_SPI_MOSI */ PAD_CFG_NC(GPP_D12),
|
||||
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
|
||||
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
|
||||
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
|
||||
/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
|
||||
/* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
|
||||
/* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
|
||||
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||
/* SPI1_IO2 */ PAD_CFG_NC(GPP_D21),
|
||||
/* SPI1_IO3 */ PAD_CFG_NC(GPP_D22),
|
||||
/* I2S_MCLK */ PAD_CFG_NC(GPP_D23),
|
||||
|
||||
/* SATAXPCI0 */ PAD_CFG_NC(GPP_E0),
|
||||
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
|
||||
/* SATAXPCIE2 */ PAD_CFG_NF(GPP_E2, UP_20K, DEEP, NF1),
|
||||
/* CPU_GP0 */ PAD_CFG_NC(GPP_E3),
|
||||
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
|
||||
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
|
||||
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
|
||||
/* CPU_GP1 */ PAD_CFG_NC(GPP_E7),
|
||||
/* SATALED# */ PAD_CFG_NC(GPP_E8),
|
||||
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
|
||||
/* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
|
||||
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
|
||||
/* USB2_OC3# */ PAD_CFG_NC(GPP_E12),
|
||||
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||
/* DDPD_HPD2 */ PAD_CFG_NC(GPP_E15),
|
||||
/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, PLTRST, NONE),
|
||||
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
|
||||
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF1),
|
||||
/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
|
||||
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, DN_20K, DEEP, NF1),
|
||||
/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP),
|
||||
/* DDPD_CTRLDATA */ PAD_CFG_TERM_GPO(GPP_E23, 1, DN_20K, DEEP),
|
||||
|
||||
/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
|
||||
/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
|
||||
/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
|
||||
/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
|
||||
/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
|
||||
/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
|
||||
/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
|
||||
/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
|
||||
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
||||
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
||||
/* I2C5_SDA */ PAD_CFG_NC(GPP_F10),
|
||||
/* I2C5_SCL */ PAD_CFG_NC(GPP_F11),
|
||||
/* EMMC_CMD */ PAD_CFG_NC(GPP_F12),
|
||||
/* EMMC_DATA0 */ PAD_CFG_NC(GPP_F13),
|
||||
/* EMMC_DATA1 */ PAD_CFG_NC(GPP_F14),
|
||||
/* EMMC_DATA2 */ PAD_CFG_NC(GPP_F15),
|
||||
/* EMMC_DATA3 */ PAD_CFG_NC(GPP_F16),
|
||||
/* EMMC_DATA4 */ PAD_CFG_NC(GPP_F17),
|
||||
/* EMMC_DATA5 */ PAD_CFG_NC(GPP_F18),
|
||||
/* EMMC_DATA6 */ PAD_CFG_NC(GPP_F19),
|
||||
/* EMMC_DATA7 */ PAD_CFG_NC(GPP_F20),
|
||||
/* EMMC_RCLK */ PAD_CFG_NC(GPP_F21),
|
||||
/* EMMC_CLK */ PAD_CFG_NC(GPP_F22),
|
||||
/* RSVD */ PAD_CFG_NC(GPP_F23),
|
||||
|
||||
/* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
|
||||
/* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
|
||||
/* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
|
||||
/* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
|
||||
/* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
|
||||
/* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
|
||||
/* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
|
||||
/* SD_WP */ PAD_CFG_NF(GPP_G7, UP_20K, DEEP, NF1),
|
||||
|
||||
/* BATLOW# */ PAD_CFG_NC(GPD0),
|
||||
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, PWROK, NF1),
|
||||
/* LAN_WAKE# */ PAD_CFG_NC(GPD2),
|
||||
/* PWRBTN# */ PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1),
|
||||
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, PWROK, NF1),
|
||||
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, PWROK, NF1),
|
||||
/* SLP_A# */ PAD_CFG_NF(GPD6, NONE, PWROK, NF1),
|
||||
/* RSVD */ PAD_CFG_NC(GPD7),
|
||||
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, PWROK, NF1),
|
||||
/* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, PWROK, NF1),
|
||||
/* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, PWROK, NF1),
|
||||
/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue