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mb/google/zork: Add INT[E-H] to FCH PIR 

INT[E-H] are required because the GNB IO-APIC maps the 32 interrupts
onto the 8 INT[A-H] that feed into the FCH PIC/IO-APIC.

BUG=b:170595019
TEST=Verify ezkinil still boots

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I9c6689e212b136f6f3c64152803ed161b2284275
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Raul E Rangel 2020-12-15 13:37:24 -07:00 committed by Felix Held
parent 7ace66e094
commit a553600e18
1 changed files with 14 additions and 2 deletions
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16
src/mainboard/google/zork/mainboard.c
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@ -76,7 +76,14 @@ static const struct pirq_struct mainboard_pirq_data[] = {
/*
* This controls the device -> IRQ routing.
* The PIC values are limited to 0,1, 3 - 12, 14, 15.
*
* Hardcoded IRQs:
* 0: timer < soc/amd/common/acpi/lpc.asl
* 1: i8042 <- ec/google/chromeec/acpi/superio.asl
* 2: cascade
* 8: rtc0 <- soc/amd/common/acpi/lpc.asl
* 9: acpi <- soc/amd/common/acpi/lpc.asl
* 12: i8042 <- ec/google/chromeec/acpi/superio.asl
*/
static const struct fch_irq_routing {
uint8_t intr_index;
@ -84,9 +91,14 @@ static const struct fch_irq_routing {
uint8_t apic_irq_num;
} fch_pirq[] = {
{ PIRQ_A, 6, 16 },
{ PIRQ_B, 6, 17 },
{ PIRQ_B, 13, 17 },
{ PIRQ_C, 14, 18 },
{ PIRQ_D, 15, 19 },
{ PIRQ_E, 15, 20 },
{ PIRQ_F, 14, 21 },
{ PIRQ_G, 13, 22 },
{ PIRQ_H, 6, 23 },
{ PIRQ_SCI, 9, 9 },
{ PIRQ_EMMC, 5, 5 },
{ PIRQ_GPIO, 7, 7 },