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soc/intel/cannonlake: Move SkipMpInit config to FSPM 

SkipMpInit UPD had ben moved from Fsp SiliconInit UPD to Fsp MemoryInit
UPD, hence change the settings in coreboot side as well. The old options
in SiliconInit get deprecated, so leave the code as is will be
harmless. Make the changes limited to coffeelake itself.

Change-Id: If968de78117068668e4f0006c412442c50658ba9
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28740
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Lijian Zhao 2018-09-25 14:27:50 -07:00 committed by Patrick Georgi
parent dc20a7d45d
commit a57447da08
1 changed files with 4 additions and 0 deletions
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4
src/soc/intel/cannonlake/romstage/romstage.c
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@ -22,6 +22,7 @@
#include <compiler.h> #include <compiler.h>
#include <console/console.h> #include <console/console.h>
#include <fsp/util.h> #include <fsp/util.h>
#include <intelblocks/chip.h>
#include <intelblocks/cse.h> #include <intelblocks/cse.h>
#include <intelblocks/pmclib.h> #include <intelblocks/pmclib.h>
#include <memory_info.h> #include <memory_info.h>
@ -175,6 +176,9 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
m_cfg->VmxEnable = 0; m_cfg->VmxEnable = 0;
else else
m_cfg->VmxEnable = config->VmxEnable; m_cfg->VmxEnable = config->VmxEnable;
#if IS_ENABLED(CONFIG_SOC_INTEL_COFFEELAKE)
m_cfg->SkipMpInit = !chip_get_fsp_mp_init();
#endif
} }
void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)