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mb/google/volteer/variants/drobit: Update DPTF parameters 

Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting.

BUG=b:177777472
BRANCH=firmware-volteer-13672.B
TEST=build test firmware and verified by thermal team.

Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927
Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Wayne3 Wang 2021-04-20 12:19:16 +08:00 committed by Nick Vaccaro
parent a590852313
commit a5761efd14
1 changed files with 8 additions and 10 deletions
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18
src/mainboard/google/volteer/variants/drobit/overridetree.cb
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@ -5,7 +5,7 @@ chip soc/intel/tigerlake
register "tcc_offset" = "8"
register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{
.tdp_pl1_override = 13,
.tdp_pl1_override = 9,
.tdp_pl2_override = 28,
.tdp_pl4 = 105,
}"
@ -63,22 +63,20 @@ chip soc/intel/tigerlake
## Active Policy
register "policies.active" = "{
[0] = {.target = DPTF_TEMP_SENSOR_1,
.thresholds = {TEMP_PCT(49, 90),
TEMP_PCT(46, 80),
TEMP_PCT(45, 70),
TEMP_PCT(44, 65),
TEMP_PCT(42, 57),
TEMP_PCT(40, 50),}}}"
.thresholds = {TEMP_PCT(49, 80),
TEMP_PCT(46, 70),
TEMP_PCT(44, 60),
TEMP_PCT(42, 50),}}}"
## Critical Policy
register "policies.critical" = "{
[0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN)}"
[0] = DPTF_CRITICAL(CPU, 100, SHUTDOWN)}"
## Power Limits Control
# 13-17W PL1 in 125mW increments, avg over 28-32s interval
# 9-17W PL1 in 125mW increments, avg over 28-32s interval
# PL2 is 28-64W, avg over 28-32s interval
register "controls.power_limits" = "{
.pl1 = {.min_power = 13000,
.pl1 = {.min_power = 9000,
.max_power = 17000,
.time_window_min = 28 * MSECS_PER_SEC,
.time_window_max = 32 * MSECS_PER_SEC,