util/inteltool: Fix ICH SPIBAR registers
The ICH7 SPIBAR offset and registers are different from later generation. ICH8 has a different offset from later generation. ICH6 has no SPI controller. Change-Id: I7691bce619089b15805114047bcb1fd121a5722b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Arthur Heymans
Martin Roth
parent
1eef32d92b
commit
a5798a9b8f
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@ -12,39 +12,57 @@ static const io_register_t pch_bios_cntl_registers[] = {
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{ 0x6, 2, "reserved" },
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};
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#define SPIBAR 0x3800
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#define ICH9_SPIBAR 0x3800
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#define ICH78_SPIBAR 0x3020
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static const io_register_t spi_bar_registers[] = {
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{ SPIBAR + 0x00, 4, "BFPR - BIOS Flash primary region" },
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{ SPIBAR + 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
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{ SPIBAR + 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
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{ SPIBAR + 0x08, 4, "FADDR - Flash Address" },
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{ SPIBAR + 0x0c, 4, "Reserved" },
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{ SPIBAR + 0x10, 4, "FDATA0" },
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{ 0x00, 4, "BFPR - BIOS Flash primary region" },
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{ 0x04, 2, "HSFSTS - Hardware Sequencing Flash Status" },
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{ 0x06, 2, "HSFCTL - Hardware Sequencing Flash Control" },
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{ 0x08, 4, "FADDR - Flash Address" },
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{ 0x0c, 4, "Reserved" },
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{ 0x10, 4, "FDATA0" },
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/* 0x10 .. 0x4f are filled with data */
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{ SPIBAR + 0x50, 4, "FRACC - Flash Region Access Permissions" },
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{ SPIBAR + 0x54, 4, "Flash Region 0" },
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{ SPIBAR + 0x58, 4, "Flash Region 1" },
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{ SPIBAR + 0x5c, 4, "Flash Region 2" },
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{ SPIBAR + 0x60, 4, "Flash Region 3" },
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{ SPIBAR + 0x64, 4, "Flash Region 4" },
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{ SPIBAR + 0x74, 4, "FPR0 Flash Protected Range 0" },
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{ SPIBAR + 0x78, 4, "FPR0 Flash Protected Range 1" },
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{ SPIBAR + 0x7c, 4, "FPR0 Flash Protected Range 2" },
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{ SPIBAR + 0x80, 4, "FPR0 Flash Protected Range 3" },
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{ SPIBAR + 0x84, 4, "FPR0 Flash Protected Range 4" },
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{ SPIBAR + 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
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{ SPIBAR + 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
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{ SPIBAR + 0x94, 2, "PREOP - Prefix opcode Configuration" },
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{ SPIBAR + 0x96, 2, "OPTYPE - Opcode Type Configuration" },
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{ SPIBAR + 0x98, 8, "OPMENU - Opcode Menu Configuration" },
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{ SPIBAR + 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
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{ SPIBAR + 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
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{ SPIBAR + 0xb8, 4, "Reserved" },
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{ SPIBAR + 0xc0, 4, "AFC - Additional Flash Control" },
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{ SPIBAR + 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
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{ SPIBAR + 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
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{ SPIBAR + 0xd0, 4, "FPB - Flash Partition Boundary" },
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{ 0x50, 4, "FRACC - Flash Region Access Permissions" },
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{ 0x54, 4, "Flash Region 0" },
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{ 0x58, 4, "Flash Region 1" },
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{ 0x5c, 4, "Flash Region 2" },
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{ 0x60, 4, "Flash Region 3" },
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{ 0x64, 4, "Flash Region 4" },
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{ 0x74, 4, "FPR0 Flash Protected Range 0" },
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{ 0x78, 4, "FPR0 Flash Protected Range 1" },
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{ 0x7c, 4, "FPR0 Flash Protected Range 2" },
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{ 0x80, 4, "FPR0 Flash Protected Range 3" },
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{ 0x84, 4, "FPR0 Flash Protected Range 4" },
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{ 0x90, 1, "SSFSTS - Software Sequencing Flash Status" },
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{ 0x91, 3, "SSFSTS - Software Sequencing Flash Status" },
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{ 0x94, 2, "PREOP - Prefix opcode Configuration" },
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{ 0x96, 2, "OPTYPE - Opcode Type Configuration" },
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{ 0x98, 8, "OPMENU - Opcode Menu Configuration" },
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{ 0xa0, 1, "BBAR - BIOS Base Address Configuration" },
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{ 0xb0, 4, "FDOC - Flash Descriptor Observability Control" },
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{ 0xb8, 4, "Reserved" },
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{ 0xc0, 4, "AFC - Additional Flash Control" },
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{ 0xc4, 4, "LVSCC - Host Lower Vendor Specific Component Capabilities" },
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{ 0xc8, 4, "UVSCC - Host Upper Vendor Specific Component Capabilities" },
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{ 0xd0, 4, "FPB - Flash Partition Boundary" },
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};
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static const io_register_t ich7_spi_bar_registers[] = {
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{ 0x00, 2, "SPIS - SPI Status" },
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{ 0x02, 2, "SPIC - SPI Control" },
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{ 0x04, 4, "SPIA - SPI Address" },
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/*
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*0x08 .. 0x47 are filled with data
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*0x48 .. 0x4f is not mentioned by datasheet
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*/
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{ 0x50, 4, "BBAR - BIOS Base Address Configuration" },
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{ 0x54, 2, "PREOP Prefix Opcode Configuration" },
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{ 0x56, 2, "OPTYPE Opcode Type Configuration" },
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{ 0x58, 8, "OPMENU Opcode Menu Configuration" },
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{ 0x60, 4, "PBR0 Protected BIOS Range 0" },
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{ 0x64, 4, "PBR1 Protected BIOS Range 1" },
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{ 0x68, 4, "PBR2 Protected BIOS Range 2" },
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};
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int print_bioscntl(struct pci_dev *sb)
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@ -100,16 +118,29 @@ int print_spibar(struct pci_dev *sb) {
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volatile uint8_t *rcba;
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uint32_t rcba_phys;
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const io_register_t *spi_register = NULL;
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uint32_t spibaroffset;
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printf("\n============= SPI Bar ==============\n\n");
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switch (sb->device_id) {
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case PCI_DEVICE_ID_INTEL_ICH6:
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printf("This southbridge does not have a SPI controller.\n");
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return 1;
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case PCI_DEVICE_ID_INTEL_ICH7:
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case PCI_DEVICE_ID_INTEL_ICH7M:
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case PCI_DEVICE_ID_INTEL_ICH7DH:
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case PCI_DEVICE_ID_INTEL_ICH7MDH:
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spibaroffset = ICH78_SPIBAR;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(ich7_spi_bar_registers);
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spi_register = ich7_spi_bar_registers;
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break;
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case PCI_DEVICE_ID_INTEL_ICH8:
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spibaroffset = ICH78_SPIBAR;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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break;
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case PCI_DEVICE_ID_INTEL_ICH8M:
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case PCI_DEVICE_ID_INTEL_ICH8ME:
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case PCI_DEVICE_ID_INTEL_ICH9DH:
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@ -171,6 +202,7 @@ int print_spibar(struct pci_dev *sb) {
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_PREM:
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case PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_BASE:
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case PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP:
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spibaroffset = ICH9_SPIBAR;
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rcba_phys = pci_read_long(sb, 0xf0) & 0xfffffffe;
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size = ARRAY_SIZE(spi_bar_registers);
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spi_register = spi_bar_registers;
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@ -197,13 +229,13 @@ int print_spibar(struct pci_dev *sb) {
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for (i = 0; i < size; i++) {
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switch(spi_register[i].size) {
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case 1:
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printf("0x%08x = %s\n", *(uint8_t *)(rcba + spi_register[i].addr), spi_register[i].name);
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printf("0x%08x = %s\n", *(uint8_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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case 2:
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printf("0x%08x = %s\n", *(uint16_t *)(rcba + spi_register[i].addr), spi_register[i].name);
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printf("0x%08x = %s\n", *(uint16_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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case 4:
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printf("0x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), spi_register[i].name);
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printf("0x%08x = %s\n", *(uint32_t *)(rcba + spibaroffset + spi_register[i].addr), spi_register[i].name);
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break;
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case 8:
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printf("0x%08x%08x = %s\n", *(uint32_t *)(rcba + spi_register[i].addr), *(uint32_t *)(rcba + spi_register[i].addr + 4), spi_register[i].name);
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