mb/google/guybrush: Update SPKR GPIO configuration for guybrush/nipperkin

For Guybrush Board Version 2, Nipperking Board Version 1,
update SPKR GPIO to match H/W schematic:
SPKR: GPIO31

For Nipperkin Board Version 2, update SPKR GPIO to
match H/W schematic:
SPKR: GPIO70

BUG=b:202992077
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage

Change-Id: I3d82292b116f53d85d9518364ffd2169bd915a7e
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59051
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Kevin Chiu 2021-11-09 23:03:35 +08:00 committed by Felix Held
parent 847a39fec7
commit a592bef03f
4 changed files with 13 additions and 7 deletions

View File

@ -66,8 +66,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPO(GPIO_29, LOW), PAD_GPO(GPIO_29, LOW),
/* ESPI_CS_L */ /* ESPI_CS_L */
PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE),
/* EN_SPKR */ /* Unused */
PAD_GPO(GPIO_31, HIGH), PAD_NC(GPIO_31),
/* Unused */ /* Unused */
PAD_NC(GPIO_32), PAD_NC(GPIO_32),
/* GPIO_33 - GPIO_39: Not available */ /* GPIO_33 - GPIO_39: Not available */
@ -83,8 +83,8 @@ static const struct soc_amd_gpio base_gpio_table[] = {
PAD_GPO(GPIO_68, HIGH), PAD_GPO(GPIO_68, HIGH),
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
PAD_GPO(GPIO_69, HIGH), PAD_GPO(GPIO_69, HIGH),
/* Unused TP27 */ /* EN_SPKR */
PAD_NC(GPIO_70), PAD_GPO(GPIO_70, HIGH),
/* GPIO_71 - GPIO_73: Not available */ /* GPIO_71 - GPIO_73: Not available */
/* Unused TP49 */ /* Unused TP49 */
PAD_NC(GPIO_74), PAD_NC(GPIO_74),

View File

@ -9,8 +9,6 @@
/* This table is used by guybrush variant with board version < 2. */ /* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = { static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {
/* Unused TP183 */
PAD_NC(GPIO_31),
/* EN_SPKR */ /* EN_SPKR */
PAD_GPO(GPIO_69, HIGH), PAD_GPO(GPIO_69, HIGH),
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
@ -37,6 +35,10 @@ static const struct soc_amd_gpio bid2_ramstage_gpio_table[] = {
PAD_NC(GPIO_85), PAD_NC(GPIO_85),
/* EN_PWR_FP */ /* EN_PWR_FP */
PAD_GPO(GPIO_32, LOW), PAD_GPO(GPIO_32, LOW),
/* EN_SPKR */
PAD_GPO(GPIO_31, HIGH),
/* Unused TP27 */
PAD_NC(GPIO_70),
}; };
static const struct soc_amd_gpio override_early_gpio_table[] = { static const struct soc_amd_gpio override_early_gpio_table[] = {

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@ -22,6 +22,10 @@ static const struct soc_amd_gpio bid1_override_gpio_table[] = {
PAD_NC(GPIO_85), PAD_NC(GPIO_85),
/* EN_PWR_FP */ /* EN_PWR_FP */
PAD_GPO(GPIO_32, LOW), PAD_GPO(GPIO_32, LOW),
/* EN_SPKR */
PAD_GPO(GPIO_31, HIGH),
/* Unused TP27 */
PAD_NC(GPIO_70),
}; };
/* This table is used by nipperkin variant with board version >= 2. */ /* This table is used by nipperkin variant with board version >= 2. */

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@ -166,7 +166,7 @@ chip soc/amd/cezanne
chip drivers/generic/max98357a chip drivers/generic/max98357a
register "hid" = ""MX98360A"" register "hid" = ""MX98360A""
register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_31)" register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_70)"
register "sdmode_delay" = "5" register "sdmode_delay" = "5"
device generic 0.1 on end device generic 0.1 on end
end end