mb/*/jslrvp/dedede: Remove hardcoding of BSP APIC ID

coreboot always assumes that BSP APIC ID will be 0 and core enumeration
logic will look for lapic id from the mainboard.

As per Intel 64 and IA-32 Architectures Software Developer’s Manual
Volume 3: 8.4.1 BSP and AP Processors, this assumption might
not hold true and we may have any other core as BSP. To handle this,
we need to remove hardcoding of APIC ID 0 from mainboard.

BUG=None
BRANCH=None
TEST=Check if there is no functional impact on the board.

Change-Id: I726d70b4ffc35a28a654abbd20c866f1410e1aee
Signed-off-by: MAULIK V VAGHELA <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
MAULIK V VAGHELA 2021-08-02 17:23:55 +05:30 committed by Subrata Banik
parent 3c0ecd57c1
commit a5a862b397
2 changed files with 2 additions and 6 deletions

View File

@ -27,9 +27,7 @@ fw_config
end end
chip soc/intel/jasperlake chip soc/intel/jasperlake
device cpu_cluster 0 on device cpu_cluster 0 on end
device lapic 0 on end
end
# GPE configuration # GPE configuration
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this

View File

@ -1,8 +1,6 @@
chip soc/intel/jasperlake chip soc/intel/jasperlake
device cpu_cluster 0 on device cpu_cluster 0 on end
device lapic 0 on end
end
# GPE configuration # GPE configuration
# Note that GPE events called out in ASL code rely on this # Note that GPE events called out in ASL code rely on this