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sb/intel/i82371eb: Clean up PM register #defines 

Remove EIO define. It is unused and means something else,
elsewhere in the tree.

Move PMIOSE bit definition next to PMREGMISC, where it actually
belongs.

Correct a number of bit defines with glaring errors.

Clarify in comments which PM register defines are in PCI config
space are which are in I/O space.

Change-Id: Ic7f2267d013403c0a519c2ee1786bd3c7f5a9708
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41637
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Keith Hui 2020-05-21 16:57:15 -04:00 committed by Patrick Georgi
parent 7cf47cfda4
commit a5a8e0962a
1 changed files with 7 additions and 8 deletions
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15
src/southbridge/intel/i82371eb/i82371eb.h
View File

@ -39,7 +39,7 @@ void i82371eb_early_init(void);
#define SMBUS_IO_BASE 0x0f00 #define SMBUS_IO_BASE 0x0f00
#define SMBHSTCFG 0xd2 /* SMBus host configuration */ #define SMBHSTCFG 0xd2 /* SMBus host configuration */
/* Power management (ACPI) */ /* Power management (ACPI) I/O ports, offset from PM_IO_BASE below */
#define PMSTS 0x00 /* Power Management Status */ #define PMSTS 0x00 /* Power Management Status */
#define PMEN 0x02 /* Power Management Resume Enable */ #define PMEN 0x02 /* Power Management Resume Enable */
#define PWRBTN_EN (1<<8) #define PWRBTN_EN (1<<8)
@ -49,8 +49,7 @@ void i82371eb_early_init(void);
#define SUS_TYP_MSK (7<<10) #define SUS_TYP_MSK (7<<10)
#define SUS_TYP_S0 (5<<10) #define SUS_TYP_S0 (5<<10)
#define SUS_TYP_S1 (4<<10) #define SUS_TYP_S1 (4<<10)
#define SUS_TYP_S2 (3<<10) #define SUS_TYP_S2 (3<<10) /* S2 may also map as 2<<10 */
//#define SUS_TYP_S2>---(2<<10)
#define SUS_TYP_S3 (1<<10) #define SUS_TYP_S3 (1<<10)
#define SUS_TYP_S5 (0<<10) #define SUS_TYP_S5 (0<<10)
#define SCI_EN (1<<0) #define SCI_EN (1<<0)
@ -64,11 +63,11 @@ void i82371eb_early_init(void);
#define EXTSMI_STS (1<<10) #define EXTSMI_STS (1<<10)
#define GSTBY_STS (1<<8) #define GSTBY_STS (1<<8)
#define GP_STS (1<<7) #define GP_STS (1<<7)
#define BM1_STS (1<<6) #define PM1_STS (1<<6)
#define APM_STS (1<<5) #define APM_STS (1<<5)
#define DEV_STS (1<<4) #define DEV_STS (1<<4)
#define BIOS_EN (1<<1) /* GBL_RLS write triggers SMI */ #define LEGACY_USB_STS (1<<1)
#define LEGACY_USB_EN (1<<0) /* Keyboard controller access triggers SMI */ #define BIOS_STS (1<<0)
#define DEVSTS 0x1c /* Device Status */ #define DEVSTS 0x1c /* Device Status */
#define GLBEN 0x20 /* Global Enable */ #define GLBEN 0x20 /* Global Enable */
#define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */ #define EXTSMI_EN (1<<10) /* EXTSMI# signal triggers SMI */
@ -86,10 +85,12 @@ void i82371eb_early_init(void);
#define GPO2 0x36 #define GPO2 0x36
#define GPO3 0x37 #define GPO3 0x37
/* Power management (ACPI) PCI registers */
#define PMBA 0x40 /* Power management base address */ #define PMBA 0x40 /* Power management base address */
#define DEFAULT_PMBASE 0xe400 #define DEFAULT_PMBASE 0xe400
#define PM_IO_BASE DEFAULT_PMBASE #define PM_IO_BASE DEFAULT_PMBASE
#define PMREGMISC 0x80 /* Miscellaneous power management */ #define PMREGMISC 0x80 /* Miscellaneous power management */
#define PMIOSE (1 << 0) /* PM I/O Space Enable */
/* Bit definitions */ /* Bit definitions */
#define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */ #define EXT_BIOS_ENABLE_1MB (1 << 9) /* 1-Meg Extended BIOS Enable */
@ -105,7 +106,5 @@ void i82371eb_early_init(void);
#define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */ #define SSDE0 (1 << 2) /* Secondary Drive 0 UDMA/33 */
#define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */ #define SSDE1 (1 << 3) /* Secondary Drive 1 UDMA/33 */
#define ISA (1 << 0) /* Select ISA */ #define ISA (1 << 0) /* Select ISA */
#define EIO (0 << 0) /* Select EIO */
#define PMIOSE (1 << 0) /* PM I/O Space Enable */
#endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */ #endif /* SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H */