src: capitalize 'APIC'
Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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@ -211,7 +211,7 @@ static void set_cpu_ops(struct device *cpu)
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cpu->ops = driver ? driver->ops : NULL;
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}
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/* Keep track of default apic ids for SMM. */
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/* Keep track of default APIC ids for SMM. */
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static int cpus_default_apic_id[CONFIG_MAX_CPUS];
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/*
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@ -22,13 +22,13 @@ Scope(\_SB) {
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/* Methods called by run-time generated SSDT Processor objects */
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Method(CPMA, 1, NotSerialized) {
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// _MAT method - create an madt apic buffer
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// _MAT method - create an madt APIC buffer
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// Arg0 = Processor ID = Local APIC ID
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// Local0 = CPON flag for this cpu
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Store(DerefOf(Index(CPON, Arg0)), Local0)
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// Local1 = Buffer (in madt apic form) to return
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// Local1 = Buffer (in madt APIC form) to return
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Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
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// Update the processor id, lapic id, and enable/disable status
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// Update the processor id, Local APIC id, and enable/disable status
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Store(Arg0, Index(Local1, 2))
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Store(Arg0, Index(Local1, 3))
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Store(Local0, Index(Local1, 4))
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@ -859,7 +859,7 @@ static void cpu_bus_scan(struct device *dev)
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* in LocalApicInitializationAtEarly() function.
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* And reference GetLocalApicIdForCore()
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*
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* Apply apic enumeration rules
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* Apply APIC enumeration rules
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* For systems with >= 16 APICs, put the IO-APICs at 0..n and
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* put the local-APICs at m..z
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*
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@ -886,7 +886,7 @@ static void cpu_bus_scan(struct device *dev)
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* in LocalApicInitializationAtEarly() function.
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* And reference GetLocalApicIdForCore()
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*
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* Apply apic enumeration rules
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* Apply APIC enumeration rules
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* For systems with >= 16 APICs, put the IO-APICs at 0..n and
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* put the local-APICs at m..z
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*
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@ -864,7 +864,7 @@ static void cpu_bus_scan(struct device *dev)
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* in LocalApicInitializationAtEarly() function.
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* And reference GetLocalApicIdForCore()
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*
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* Apply apic enumeration rules
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* Apply APIC enumeration rules
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* For systems with >= 16 APICs, put the IO-APICs at 0..n and
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* put the local-APICs at m..z
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*
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@ -871,7 +871,7 @@ static void cpu_bus_scan(struct device *dev)
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* in LocalApicInitializationAtEarly() function.
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* And reference GetLocalApicIdForCore()
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*
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* Apply apic enumeration rules
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* Apply APIC enumeration rules
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* For systems with >= 16 APICs, put the IO-APICs at 0..n and
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* put the local-APICs at m..z
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*
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@ -1130,7 +1130,7 @@ static void cpu_bus_scan(struct device *dev)
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* in LocalApicInitializationAtEarly() function.
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* And reference GetLocalApicIdForCore()
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*
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* Apply apic enumeration rules
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* Apply APIC enumeration rules
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* For systems with >= 16 APICs, put the IO-APICs at 0..n and
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* put the local-APICs at m..z
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*
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@ -196,49 +196,49 @@
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.io_sel = GPIO_DIR_INPUT, \
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.is_gpio = 1 }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ \
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{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT, }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ_LEVELHIGH_NO_PULL \
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{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT, }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ_LEVELLOW_PU_20K \
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{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT, }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ_EDGELOW_PU_20K \
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{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT, }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ_EDGEHIGH_PD_20K \
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{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT, }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ_EDGELOW_PD_20K \
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{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
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.pad_conf1 = PAD_CONFIG1_DEFAULT, \
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.pad_val = PAD_VAL_INPUT, }
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/* Direct / dedicated IRQ input - pass signal directly to apic */
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/* Direct / dedicated IRQ input - pass signal directly to APIC */
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#define GPIO_DIRQ_EDGEBOTH_PU_20K \
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{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
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| PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \
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@ -71,7 +71,7 @@ static void __unused southbridge_trigger_smi(void)
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* Using the local APIC is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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@ -305,7 +305,7 @@ static void aseg_smm_relocate(void)
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* Using the local APIC is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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@ -111,7 +111,7 @@ static void aseg_smm_relocate(void)
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* Using the local APIC is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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@ -11,7 +11,7 @@
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* GNU General Public License for more details.
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*/
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/* for io apic 1461 */
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/* for io APIC 1461 */
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#define MBAR 0x10
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#define ABAR 0x40
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@ -43,8 +43,8 @@ static void p64h2_ioapic_init(struct device *dev)
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uint32_t memoryBase;
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int apic_index, apic_id;
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volatile uint32_t *pIndexRegister; /* io apic io memory space command address */
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volatile uint32_t *pWindowRegister; /* io apic io memory space data address */
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volatile uint32_t *pIndexRegister; /* io APIC io memory space command address */
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volatile uint32_t *pWindowRegister; /* io APIC io memory space data address */
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apic_index = num_p64h2_ioapics;
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num_p64h2_ioapics++;
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@ -76,7 +76,7 @@ static void __unused southbridge_trigger_smi(void)
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* - Writes to io 0xb2 (APMC)
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* - Writes to the Local Apic ICR with Delivery mode SMI.
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*
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* Using the local apic is a bit more tricky. According to
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* Using the local APIC is a bit more tricky. According to
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* AMD Family 11 Processor BKDG no destination shorthand must be
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* used.
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* The whole SMM initialization is quite a bit hardware specific, so
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