src: capitalize 'APIC'

Change-Id: I487fb53bb2b011d214f002fc200ade2f128a4cc6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39030
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/arch/x86/cpu.c

@@ -211,7 +211,7 @@ static void set_cpu_ops(struct device *cpu)
 	cpu->ops = driver ? driver->ops : NULL;
 }
 
-/* Keep track of default apic ids for SMM. */
+/* Keep track of default APIC ids for SMM. */
 static int cpus_default_apic_id[CONFIG_MAX_CPUS];
 
 /*

src/mainboard/emulation/qemu-i440fx/acpi/cpu-hotplug.asl

@@ -22,13 +22,13 @@ Scope(\_SB) {
 
     /* Methods called by run-time generated SSDT Processor objects */
     Method(CPMA, 1, NotSerialized) {
-        // _MAT method - create an madt apic buffer
+        // _MAT method - create an madt APIC buffer
         // Arg0 = Processor ID = Local APIC ID
         // Local0 = CPON flag for this cpu
         Store(DerefOf(Index(CPON, Arg0)), Local0)
-        // Local1 = Buffer (in madt apic form) to return
+        // Local1 = Buffer (in madt APIC form) to return
         Store(Buffer(8) {0x00, 0x08, 0x00, 0x00, 0x00, 0, 0, 0}, Local1)
-        // Update the processor id, lapic id, and enable/disable status
+        // Update the processor id, Local APIC id, and enable/disable status
         Store(Arg0, Index(Local1, 2))
         Store(Arg0, Index(Local1, 3))
         Store(Local0, Index(Local1, 4))

src/northbridge/amd/agesa/family15tn/northbridge.c

@@ -859,7 +859,7 @@ static void cpu_bus_scan(struct device *dev)
 			 * in LocalApicInitializationAtEarly() function.
 			 * And reference GetLocalApicIdForCore()
 			 *
-			 * Apply apic enumeration rules
+			 * Apply APIC enumeration rules
 			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
 			 * put the local-APICs at m..z
 			 *

src/northbridge/amd/agesa/family16kb/northbridge.c

@@ -886,7 +886,7 @@ static void cpu_bus_scan(struct device *dev)
 			 * in LocalApicInitializationAtEarly() function.
 			 * And reference GetLocalApicIdForCore()
 			 *
-			 * Apply apic enumeration rules
+			 * Apply APIC enumeration rules
 			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
 			 * put the local-APICs at m..z
 			 *

src/northbridge/amd/pi/00630F01/northbridge.c

@@ -864,7 +864,7 @@ static void cpu_bus_scan(struct device *dev)
 			 * in LocalApicInitializationAtEarly() function.
 			 * And reference GetLocalApicIdForCore()
 			 *
-			 * Apply apic enumeration rules
+			 * Apply APIC enumeration rules
 			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
 			 * put the local-APICs at m..z
 			 *

src/northbridge/amd/pi/00660F01/northbridge.c

@@ -871,7 +871,7 @@ static void cpu_bus_scan(struct device *dev)
 			 * in LocalApicInitializationAtEarly() function.
 			 * And reference GetLocalApicIdForCore()
 			 *
-			 * Apply apic enumeration rules
+			 * Apply APIC enumeration rules
 			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
 			 * put the local-APICs at m..z
 			 *

src/northbridge/amd/pi/00730F01/northbridge.c

@@ -1130,7 +1130,7 @@ static void cpu_bus_scan(struct device *dev)
 			 * in LocalApicInitializationAtEarly() function.
 			 * And reference GetLocalApicIdForCore()
 			 *
-			 * Apply apic enumeration rules
+			 * Apply APIC enumeration rules
 			 * For systems with >= 16 APICs, put the IO-APICs at 0..n and
 			 * put the local-APICs at m..z
 			 *

src/soc/intel/baytrail/include/soc/gpio.h

@@ -196,49 +196,49 @@
 	  .io_sel    = GPIO_DIR_INPUT, \
 	  .is_gpio   = 1 }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ \
 	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ_LEVELHIGH_NO_PULL \
 	{ .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_LEVEL_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ_LEVELLOW_PU_20K \
 	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_LEVEL_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ_EDGELOW_PU_20K \
 	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ_EDGEHIGH_PD_20K \
 	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ | PAD_EDGE_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ_EDGELOW_PD_20K \
 	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_DOWN | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TNE_IRQ | PAD_EDGE_IRQ, \
 	  .pad_conf1 = PAD_CONFIG1_DEFAULT, \
 	  .pad_val   = PAD_VAL_INPUT, }
 
-/* Direct / dedicated IRQ input - pass signal directly to apic */
+/* Direct / dedicated IRQ input - pass signal directly to APIC */
 #define GPIO_DIRQ_EDGEBOTH_PU_20K \
 	{ .pad_conf0 = PAD_PU_20K | PAD_PULL_UP | PAD_CONFIG0_DEFAULT \
 		     | PAD_FUNC0 | PAD_IRQ_EN | PAD_TPE_IRQ| PAD_TNE_IRQ | PAD_EDGE_IRQ, \

src/soc/intel/broadwell/smi.c

@@ -71,7 +71,7 @@ static void __unused southbridge_trigger_smi(void)
 	 *  - Writes to io 0xb2 (APMC)
 	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
 	 *
-	 * Using the local apic is a bit more tricky. According to
+	 * Using the local APIC is a bit more tricky. According to
 	 * AMD Family 11 Processor BKDG no destination shorthand must be
 	 * used.
 	 * The whole SMM initialization is quite a bit hardware specific, so

src/southbridge/intel/i82801dx/smi.c

@@ -305,7 +305,7 @@ static void aseg_smm_relocate(void)
 	 *  - Writes to io 0xb2 (APMC)
 	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
 	 *
-	 * Using the local apic is a bit more tricky. According to
+	 * Using the local APIC is a bit more tricky. According to
 	 * AMD Family 11 Processor BKDG no destination shorthand must be
 	 * used.
 	 * The whole SMM initialization is quite a bit hardware specific, so

src/southbridge/intel/i82801ix/smi.c

@@ -111,7 +111,7 @@ static void aseg_smm_relocate(void)
 	 *  - Writes to io 0xb2 (APMC)
 	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
 	 *
-	 * Using the local apic is a bit more tricky. According to
+	 * Using the local APIC is a bit more tricky. According to
 	 * AMD Family 11 Processor BKDG no destination shorthand must be
 	 * used.
 	 * The whole SMM initialization is quite a bit hardware specific, so

src/southbridge/intel/i82870/82870.h

@@ -11,7 +11,7 @@
  * GNU General Public License for more details.
  */
 
-/* for io apic 1461 */
+/* for io APIC 1461 */
 #define MBAR		0x10
 #define ABAR		0x40
 

src/southbridge/intel/i82870/ioapic.c

@@ -43,8 +43,8 @@ static void p64h2_ioapic_init(struct device *dev)
 	uint32_t memoryBase;
 	int apic_index, apic_id;
 
-	volatile uint32_t *pIndexRegister;    /* io apic io memory space command address */
-	volatile uint32_t *pWindowRegister;    /* io apic io memory space data address */
+	volatile uint32_t *pIndexRegister;    /* io APIC io memory space command address */
+	volatile uint32_t *pWindowRegister;    /* io APIC io memory space data address */
 
 	apic_index = num_p64h2_ioapics;
 	num_p64h2_ioapics++;

src/southbridge/intel/lynxpoint/smi.c

@@ -76,7 +76,7 @@ static void  __unused southbridge_trigger_smi(void)
 	 *  - Writes to io 0xb2 (APMC)
 	 *  - Writes to the Local Apic ICR with Delivery mode SMI.
 	 *
-	 * Using the local apic is a bit more tricky. According to
+	 * Using the local APIC is a bit more tricky. According to
 	 * AMD Family 11 Processor BKDG no destination shorthand must be
 	 * used.
 	 * The whole SMM initialization is quite a bit hardware specific, so