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riscv: separately define stack locations at different stages 

BOOTBLOCK/ROMSTAGE run in CAR/scratchpad. When RAMSTAGE begins
execution will enable cache, then CAR will disappear. So the
Stack will be separated.

Change-Id: I37a0c1928052cabf61ba5c25b440363b75726782
Signed-off-by: Xiang Wang <wxjstz@126.com>
Reviewed-on: https://review.coreboot.org/28383
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
Xiang Wang 2018-08-29 14:59:32 +08:00 committed by Martin Roth
parent 0186912f9e
commit a5b265bb0c
2 changed files with 17 additions and 2 deletions
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14
src/arch/riscv/include/arch/memlayout.h
View File

@ -20,6 +20,20 @@
#define STACK(addr, size) REGION(stack, addr, size, 4096)
#if defined(__PRE_RAM__)
#define CAR_STACK(addr, size) \
REGION(car_stack, addr, size, 4K) \
ALIAS_REGION(car_stack, stack)
#define MEM_STACK(addr, size) \
REGION(mem_stack, addr, size, 4K)
#else
#define CAR_STACK(addr, size) \
REGION(car_stack, addr, size, 4K)
#define MEM_STACK(addr, size) \
REGION(mem_stack, addr, size, 4K) \
ALIAS_REGION(mem_stack, stack)
#endif
/* TODO: Need to add DMA_COHERENT region like on ARM? */
#endif /* __ARCH_MEMLAYOUT_H */

5
src/soc/sifive/fu540/include/soc/memlayout.ld
View File

@ -25,11 +25,12 @@ SECTIONS
{
L2LIM_START(FU540_L2LIM)
BOOTBLOCK(FU540_L2LIM, 64K)
STACK(FU540_L2LIM + 64K, 4K)
PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 68K, 8K)
CAR_STACK(FU540_L2LIM + 64K, 20K)
PRERAM_CBMEM_CONSOLE(FU540_L2LIM + 84K, 8K)
ROMSTAGE(FU540_L2LIM + 128K, 128K)
L2LIM_END(FU540_L2LIM + 2M)
DRAM_START(FU540_DRAM)
RAMSTAGE(FU540_DRAM, 256K)
MEM_STACK(FU540_DRAM + 256K, 20K)
}