arch/riscv: Update encoding.h and adjust related code
Update encoding.h to the version shipped with spike commit
0185d36 ("Merge pull request #165 from riscv/small_progbuf"),
and copy the license header from the LICENSE file.
Change-Id: I517042e5865986e88a589dc8623745f8d584d6b8
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/23773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Jonathan Neuschäfer
Martin Roth
parent
042a8336f3
commit
a5c49b8d43
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@ -1,6 +1,6 @@
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/*
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* Copyright (c) 2016, The Regents of the University of California (Regents).
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* All Rights Reserved.
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* Copyright (c) 2010-2017, The Regents of the University of California
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* (Regents). All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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@ -42,17 +42,16 @@
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#define MSTATUS_FS 0x00006000
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#define MSTATUS_XS 0x00018000
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#define MSTATUS_MPRV 0x00020000
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#define MSTATUS_PUM 0x00040000
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#define MSTATUS_SUM 0x00040000
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#define MSTATUS_MXR 0x00080000
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#define MSTATUS_VM 0x1F000000
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#define MSTATUS_TVM 0x00100000
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#define MSTATUS_TW 0x00200000
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#define MSTATUS_TSR 0x00400000
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#define MSTATUS32_SD 0x80000000
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#define MSTATUS_UXL 0x0000000300000000
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#define MSTATUS_SXL 0x0000000C00000000
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#define MSTATUS64_SD 0x8000000000000000
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#define MIE_UTIE 0x00000010
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#define MIE_STIE 0x00000020
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#define MIE_HTIE 0x00000040
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#define MIE_MTIE 0x00000080
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#define SSTATUS_UIE 0x00000001
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#define SSTATUS_SIE 0x00000002
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#define SSTATUS_UPIE 0x00000010
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@ -60,8 +59,10 @@
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#define SSTATUS_SPP 0x00000100
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#define SSTATUS_FS 0x00006000
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#define SSTATUS_XS 0x00018000
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#define SSTATUS_PUM 0x00040000
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#define SSTATUS_SUM 0x00040000
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#define SSTATUS_MXR 0x00080000
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#define SSTATUS32_SD 0x80000000
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#define SSTATUS_UXL 0x0000000300000000
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#define SSTATUS64_SD 0x8000000000000000
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#define DCSR_XDEBUGVER (3U<<30)
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@ -131,19 +132,36 @@
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#define SIP_SSIP MIP_SSIP
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#define SIP_STIP MIP_STIP
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#define SIE_STIE MIE_STIE
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#define PRV_U 0
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#define PRV_S 1
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#define PRV_H 2
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#define PRV_M 3
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#define VM_MBARE 0
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#define VM_MBB 1
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#define VM_MBBID 2
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#define VM_SV32 8
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#define VM_SV39 9
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#define VM_SV48 10
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#define SATP32_MODE 0x80000000
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#define SATP32_ASID 0x7FC00000
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#define SATP32_PPN 0x003FFFFF
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#define SATP64_MODE 0xF000000000000000
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#define SATP64_ASID 0x0FFFF00000000000
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#define SATP64_PPN 0x00000FFFFFFFFFFF
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#define SATP_MODE_OFF 0
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#define SATP_MODE_SV32 1
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#define SATP_MODE_SV39 8
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#define SATP_MODE_SV48 9
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#define SATP_MODE_SV57 10
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#define SATP_MODE_SV64 11
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#define PMP_R 0x01
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#define PMP_W 0x02
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#define PMP_X 0x04
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#define PMP_A 0x18
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#define PMP_L 0x80
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#define PMP_SHIFT 2
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#define PMP_TOR 0x08
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#define PMP_NA4 0x10
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#define PMP_NAPOT 0x18
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#define IRQ_S_SOFT 1
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#define IRQ_H_SOFT 2
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@ -158,9 +176,8 @@
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#define IRQ_HOST 13
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#define DEFAULT_RSTVEC 0x00001000
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#define DEFAULT_NMIVEC 0x00001004
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#define DEFAULT_MTVEC 0x00001010
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#define CONFIG_STRING_ADDR 0x0000100C
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#define CLINT_BASE 0x02000000
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#define CLINT_SIZE 0x000c0000
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#define EXT_IO_BASE 0x40000000
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#define DRAM_BASE 0x80000000
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@ -181,14 +198,16 @@
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#ifdef __riscv
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#ifdef __riscv64
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#if __riscv_xlen == 64
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# define MSTATUS_SD MSTATUS64_SD
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# define SSTATUS_SD SSTATUS64_SD
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# define RISCV_PGLEVEL_BITS 9
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# define SATP_MODE SATP64_MODE
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#else
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# define MSTATUS_SD MSTATUS32_SD
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# define SSTATUS_SD SSTATUS32_SD
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# define RISCV_PGLEVEL_BITS 10
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# define SATP_MODE SATP32_MODE
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#endif
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#define RISCV_PGSHIFT 12
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#define RISCV_PGSIZE (1 << RISCV_PGSHIFT)
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@ -202,30 +221,18 @@
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__tmp; })
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#define write_csr(reg, val) ({ \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
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else \
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asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
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asm volatile ("csrw " #reg ", %0" :: "rK"(val)); })
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#define swap_csr(reg, val) ({ unsigned long __tmp; \
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if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \
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else \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \
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asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "rK"(val)); \
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__tmp; })
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#define set_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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__tmp; })
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#define clear_csr(reg, bit) ({ unsigned long __tmp; \
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if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \
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else \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \
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asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "rK"(bit)); \
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__tmp; })
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#define rdtime() read_csr(time)
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@ -239,7 +246,7 @@
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#endif
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#endif
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/* Automatically generated by parse-opcodes */
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/* Automatically generated by parse-opcodes. */
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#ifndef RISCV_ENCODING_H
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#define RISCV_ENCODING_H
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#define MATCH_BEQ 0x63
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@ -422,14 +429,12 @@
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#define MASK_URET 0xffffffff
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#define MATCH_SRET 0x10200073
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#define MASK_SRET 0xffffffff
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#define MATCH_HRET 0x20200073
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#define MASK_HRET 0xffffffff
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#define MATCH_MRET 0x30200073
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#define MASK_MRET 0xffffffff
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#define MATCH_DRET 0x7b200073
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#define MASK_DRET 0xffffffff
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#define MATCH_SFENCE_VM 0x10400073
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#define MASK_SFENCE_VM 0xfff07fff
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#define MATCH_SFENCE_VMA 0x12000073
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#define MASK_SFENCE_VMA 0xfe007fff
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#define MATCH_WFI 0x10500073
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#define MASK_WFI 0xffffffff
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#define MATCH_CSRRW 0x1073
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@ -488,6 +493,34 @@
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#define MASK_FCVT_D_S 0xfff0007f
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#define MATCH_FSQRT_D 0x5a000053
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#define MASK_FSQRT_D 0xfff0007f
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#define MATCH_FADD_Q 0x6000053
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#define MASK_FADD_Q 0xfe00007f
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#define MATCH_FSUB_Q 0xe000053
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#define MASK_FSUB_Q 0xfe00007f
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#define MATCH_FMUL_Q 0x16000053
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#define MASK_FMUL_Q 0xfe00007f
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#define MATCH_FDIV_Q 0x1e000053
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#define MASK_FDIV_Q 0xfe00007f
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#define MATCH_FSGNJ_Q 0x26000053
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#define MASK_FSGNJ_Q 0xfe00707f
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#define MATCH_FSGNJN_Q 0x26001053
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#define MASK_FSGNJN_Q 0xfe00707f
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#define MATCH_FSGNJX_Q 0x26002053
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#define MASK_FSGNJX_Q 0xfe00707f
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#define MATCH_FMIN_Q 0x2e000053
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#define MASK_FMIN_Q 0xfe00707f
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#define MATCH_FMAX_Q 0x2e001053
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#define MASK_FMAX_Q 0xfe00707f
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#define MATCH_FCVT_S_Q 0x40300053
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#define MASK_FCVT_S_Q 0xfff0007f
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#define MATCH_FCVT_Q_S 0x46000053
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#define MASK_FCVT_Q_S 0xfff0007f
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#define MATCH_FCVT_D_Q 0x42300053
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#define MASK_FCVT_D_Q 0xfff0007f
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#define MATCH_FCVT_Q_D 0x46100053
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#define MASK_FCVT_Q_D 0xfff0007f
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#define MATCH_FSQRT_Q 0x5e000053
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#define MASK_FSQRT_Q 0xfff0007f
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#define MATCH_FLE_S 0xa0000053
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#define MASK_FLE_S 0xfe00707f
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#define MATCH_FLT_S 0xa0001053
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@ -500,6 +533,12 @@
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#define MASK_FLT_D 0xfe00707f
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#define MATCH_FEQ_D 0xa2002053
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#define MASK_FEQ_D 0xfe00707f
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#define MATCH_FLE_Q 0xa6000053
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#define MASK_FLE_Q 0xfe00707f
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#define MATCH_FLT_Q 0xa6001053
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#define MASK_FLT_Q 0xfe00707f
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#define MATCH_FEQ_Q 0xa6002053
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#define MASK_FEQ_Q 0xfe00707f
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#define MATCH_FCVT_W_S 0xc0000053
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#define MASK_FCVT_W_S 0xfff0007f
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#define MATCH_FCVT_WU_S 0xc0100053
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@ -508,8 +547,8 @@
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#define MASK_FCVT_L_S 0xfff0007f
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#define MATCH_FCVT_LU_S 0xc0300053
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#define MASK_FCVT_LU_S 0xfff0007f
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#define MATCH_FMV_X_S 0xe0000053
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#define MASK_FMV_X_S 0xfff0707f
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#define MATCH_FMV_X_W 0xe0000053
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#define MASK_FMV_X_W 0xfff0707f
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#define MATCH_FCLASS_S 0xe0001053
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#define MASK_FCLASS_S 0xfff0707f
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#define MATCH_FCVT_W_D 0xc2000053
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@ -524,6 +563,18 @@
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#define MASK_FMV_X_D 0xfff0707f
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#define MATCH_FCLASS_D 0xe2001053
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#define MASK_FCLASS_D 0xfff0707f
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#define MATCH_FCVT_W_Q 0xc6000053
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#define MASK_FCVT_W_Q 0xfff0007f
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#define MATCH_FCVT_WU_Q 0xc6100053
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#define MASK_FCVT_WU_Q 0xfff0007f
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#define MATCH_FCVT_L_Q 0xc6200053
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#define MASK_FCVT_L_Q 0xfff0007f
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#define MATCH_FCVT_LU_Q 0xc6300053
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#define MASK_FCVT_LU_Q 0xfff0007f
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#define MATCH_FMV_X_Q 0xe6000053
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#define MASK_FMV_X_Q 0xfff0707f
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#define MATCH_FCLASS_Q 0xe6001053
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#define MASK_FCLASS_Q 0xfff0707f
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#define MATCH_FCVT_S_W 0xd0000053
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#define MASK_FCVT_S_W 0xfff0007f
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#define MATCH_FCVT_S_WU 0xd0100053
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@ -532,8 +583,8 @@
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#define MASK_FCVT_S_L 0xfff0007f
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#define MATCH_FCVT_S_LU 0xd0300053
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#define MASK_FCVT_S_LU 0xfff0007f
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#define MATCH_FMV_S_X 0xf0000053
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#define MASK_FMV_S_X 0xfff0707f
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#define MATCH_FMV_W_X 0xf0000053
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#define MASK_FMV_W_X 0xfff0707f
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#define MATCH_FCVT_D_W 0xd2000053
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#define MASK_FCVT_D_W 0xfff0007f
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#define MATCH_FCVT_D_WU 0xd2100053
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@ -544,14 +595,28 @@
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#define MASK_FCVT_D_LU 0xfff0007f
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#define MATCH_FMV_D_X 0xf2000053
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#define MASK_FMV_D_X 0xfff0707f
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#define MATCH_FCVT_Q_W 0xd6000053
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#define MASK_FCVT_Q_W 0xfff0007f
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#define MATCH_FCVT_Q_WU 0xd6100053
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#define MASK_FCVT_Q_WU 0xfff0007f
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#define MATCH_FCVT_Q_L 0xd6200053
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#define MASK_FCVT_Q_L 0xfff0007f
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#define MATCH_FCVT_Q_LU 0xd6300053
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#define MASK_FCVT_Q_LU 0xfff0007f
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#define MATCH_FMV_Q_X 0xf6000053
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#define MASK_FMV_Q_X 0xfff0707f
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#define MATCH_FLW 0x2007
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#define MASK_FLW 0x707f
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#define MATCH_FLD 0x3007
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#define MASK_FLD 0x707f
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#define MATCH_FLQ 0x4007
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#define MASK_FLQ 0x707f
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#define MATCH_FSW 0x2027
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#define MASK_FSW 0x707f
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#define MATCH_FSD 0x3027
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#define MASK_FSD 0x707f
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#define MATCH_FSQ 0x4027
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#define MASK_FSQ 0x707f
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#define MATCH_FMADD_S 0x43
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#define MASK_FMADD_S 0x600007f
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#define MATCH_FMSUB_S 0x47
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@ -568,6 +633,14 @@
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#define MASK_FNMSUB_D 0x600007f
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#define MATCH_FNMADD_D 0x200004f
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#define MASK_FNMADD_D 0x600007f
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#define MATCH_FMADD_Q 0x6000043
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#define MASK_FMADD_Q 0x600007f
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#define MATCH_FMSUB_Q 0x6000047
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#define MASK_FMSUB_Q 0x600007f
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#define MATCH_FNMSUB_Q 0x600004b
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#define MASK_FNMSUB_Q 0x600007f
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#define MATCH_FNMADD_Q 0x600004f
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#define MASK_FNMADD_Q 0x600007f
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#define MATCH_C_NOP 0x1
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#define MASK_C_NOP 0xffff
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#define MATCH_C_ADDI16SP 0x6101
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@ -738,23 +811,45 @@
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_SBADADDR 0x143
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SPTBR 0x180
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#define CSR_SATP 0x180
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MEDELEG 0x302
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#define CSR_MIDELEG 0x303
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MCOUNTEREN 0x306
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MBADADDR 0x343
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPCFG1 0x3a1
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#define CSR_PMPCFG2 0x3a2
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#define CSR_PMPCFG3 0x3a3
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#define CSR_PMPADDR0 0x3b0
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#define CSR_PMPADDR1 0x3b1
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#define CSR_PMPADDR2 0x3b2
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#define CSR_PMPADDR3 0x3b3
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#define CSR_PMPADDR4 0x3b4
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#define CSR_PMPADDR5 0x3b5
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#define CSR_PMPADDR6 0x3b6
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#define CSR_PMPADDR7 0x3b7
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#define CSR_PMPADDR8 0x3b8
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#define CSR_PMPADDR9 0x3b9
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#define CSR_PMPADDR10 0x3ba
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#define CSR_PMPADDR11 0x3bb
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#define CSR_PMPADDR12 0x3bc
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#define CSR_PMPADDR13 0x3bd
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#define CSR_PMPADDR14 0x3be
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#define CSR_PMPADDR15 0x3bf
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#define CSR_TSELECT 0x7a0
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#define CSR_TDATA1 0x7a1
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#define CSR_TDATA2 0x7a2
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@ -793,8 +888,6 @@
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#define CSR_MHPMCOUNTER29 0xb1d
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#define CSR_MHPMCOUNTER30 0xb1e
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#define CSR_MHPMCOUNTER31 0xb1f
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#define CSR_MUCOUNTEREN 0x320
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#define CSR_MSCOUNTEREN 0x321
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#define CSR_MHPMEVENT3 0x323
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#define CSR_MHPMEVENT4 0x324
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#define CSR_MHPMEVENT5 0x325
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|
|
@ -892,17 +985,20 @@
|
|||
#define CSR_MHPMCOUNTER30H 0xb9e
|
||||
#define CSR_MHPMCOUNTER31H 0xb9f
|
||||
#define CAUSE_MISALIGNED_FETCH 0x0
|
||||
#define CAUSE_FAULT_FETCH 0x1
|
||||
#define CAUSE_FETCH_ACCESS 0x1
|
||||
#define CAUSE_ILLEGAL_INSTRUCTION 0x2
|
||||
#define CAUSE_BREAKPOINT 0x3
|
||||
#define CAUSE_MISALIGNED_LOAD 0x4
|
||||
#define CAUSE_FAULT_LOAD 0x5
|
||||
#define CAUSE_LOAD_ACCESS 0x5
|
||||
#define CAUSE_MISALIGNED_STORE 0x6
|
||||
#define CAUSE_FAULT_STORE 0x7
|
||||
#define CAUSE_STORE_ACCESS 0x7
|
||||
#define CAUSE_USER_ECALL 0x8
|
||||
#define CAUSE_SUPERVISOR_ECALL 0x9
|
||||
#define CAUSE_HYPERVISOR_ECALL 0xa
|
||||
#define CAUSE_MACHINE_ECALL 0xb
|
||||
#define CAUSE_FETCH_PAGE_FAULT 0xc
|
||||
#define CAUSE_LOAD_PAGE_FAULT 0xd
|
||||
#define CAUSE_STORE_PAGE_FAULT 0xf
|
||||
#endif
|
||||
#ifdef DECLARE_INSN
|
||||
DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ)
|
||||
|
|
@ -995,10 +1091,9 @@ DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL)
|
|||
DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK)
|
||||
DECLARE_INSN(uret, MATCH_URET, MASK_URET)
|
||||
DECLARE_INSN(sret, MATCH_SRET, MASK_SRET)
|
||||
DECLARE_INSN(hret, MATCH_HRET, MASK_HRET)
|
||||
DECLARE_INSN(mret, MATCH_MRET, MASK_MRET)
|
||||
DECLARE_INSN(dret, MATCH_DRET, MASK_DRET)
|
||||
DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM)
|
||||
DECLARE_INSN(sfence_vma, MATCH_SFENCE_VMA, MASK_SFENCE_VMA)
|
||||
DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI)
|
||||
DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW)
|
||||
DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS)
|
||||
|
|
@ -1028,17 +1123,34 @@ DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D)
|
|||
DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D)
|
||||
DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S)
|
||||
DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D)
|
||||
DECLARE_INSN(fadd_q, MATCH_FADD_Q, MASK_FADD_Q)
|
||||
DECLARE_INSN(fsub_q, MATCH_FSUB_Q, MASK_FSUB_Q)
|
||||
DECLARE_INSN(fmul_q, MATCH_FMUL_Q, MASK_FMUL_Q)
|
||||
DECLARE_INSN(fdiv_q, MATCH_FDIV_Q, MASK_FDIV_Q)
|
||||
DECLARE_INSN(fsgnj_q, MATCH_FSGNJ_Q, MASK_FSGNJ_Q)
|
||||
DECLARE_INSN(fsgnjn_q, MATCH_FSGNJN_Q, MASK_FSGNJN_Q)
|
||||
DECLARE_INSN(fsgnjx_q, MATCH_FSGNJX_Q, MASK_FSGNJX_Q)
|
||||
DECLARE_INSN(fmin_q, MATCH_FMIN_Q, MASK_FMIN_Q)
|
||||
DECLARE_INSN(fmax_q, MATCH_FMAX_Q, MASK_FMAX_Q)
|
||||
DECLARE_INSN(fcvt_s_q, MATCH_FCVT_S_Q, MASK_FCVT_S_Q)
|
||||
DECLARE_INSN(fcvt_q_s, MATCH_FCVT_Q_S, MASK_FCVT_Q_S)
|
||||
DECLARE_INSN(fcvt_d_q, MATCH_FCVT_D_Q, MASK_FCVT_D_Q)
|
||||
DECLARE_INSN(fcvt_q_d, MATCH_FCVT_Q_D, MASK_FCVT_Q_D)
|
||||
DECLARE_INSN(fsqrt_q, MATCH_FSQRT_Q, MASK_FSQRT_Q)
|
||||
DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S)
|
||||
DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S)
|
||||
DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S)
|
||||
DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D)
|
||||
DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D)
|
||||
DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D)
|
||||
DECLARE_INSN(fle_q, MATCH_FLE_Q, MASK_FLE_Q)
|
||||
DECLARE_INSN(flt_q, MATCH_FLT_Q, MASK_FLT_Q)
|
||||
DECLARE_INSN(feq_q, MATCH_FEQ_Q, MASK_FEQ_Q)
|
||||
DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S)
|
||||
DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S)
|
||||
DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S)
|
||||
DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S)
|
||||
DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S)
|
||||
DECLARE_INSN(fmv_x_w, MATCH_FMV_X_W, MASK_FMV_X_W)
|
||||
DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S)
|
||||
DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D)
|
||||
DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D)
|
||||
|
|
@ -1046,20 +1158,33 @@ DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D)
|
|||
DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D)
|
||||
DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D)
|
||||
DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D)
|
||||
DECLARE_INSN(fcvt_w_q, MATCH_FCVT_W_Q, MASK_FCVT_W_Q)
|
||||
DECLARE_INSN(fcvt_wu_q, MATCH_FCVT_WU_Q, MASK_FCVT_WU_Q)
|
||||
DECLARE_INSN(fcvt_l_q, MATCH_FCVT_L_Q, MASK_FCVT_L_Q)
|
||||
DECLARE_INSN(fcvt_lu_q, MATCH_FCVT_LU_Q, MASK_FCVT_LU_Q)
|
||||
DECLARE_INSN(fmv_x_q, MATCH_FMV_X_Q, MASK_FMV_X_Q)
|
||||
DECLARE_INSN(fclass_q, MATCH_FCLASS_Q, MASK_FCLASS_Q)
|
||||
DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W)
|
||||
DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU)
|
||||
DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L)
|
||||
DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU)
|
||||
DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X)
|
||||
DECLARE_INSN(fmv_w_x, MATCH_FMV_W_X, MASK_FMV_W_X)
|
||||
DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W)
|
||||
DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU)
|
||||
DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L)
|
||||
DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU)
|
||||
DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X)
|
||||
DECLARE_INSN(fcvt_q_w, MATCH_FCVT_Q_W, MASK_FCVT_Q_W)
|
||||
DECLARE_INSN(fcvt_q_wu, MATCH_FCVT_Q_WU, MASK_FCVT_Q_WU)
|
||||
DECLARE_INSN(fcvt_q_l, MATCH_FCVT_Q_L, MASK_FCVT_Q_L)
|
||||
DECLARE_INSN(fcvt_q_lu, MATCH_FCVT_Q_LU, MASK_FCVT_Q_LU)
|
||||
DECLARE_INSN(fmv_q_x, MATCH_FMV_Q_X, MASK_FMV_Q_X)
|
||||
DECLARE_INSN(flw, MATCH_FLW, MASK_FLW)
|
||||
DECLARE_INSN(fld, MATCH_FLD, MASK_FLD)
|
||||
DECLARE_INSN(flq, MATCH_FLQ, MASK_FLQ)
|
||||
DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW)
|
||||
DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD)
|
||||
DECLARE_INSN(fsq, MATCH_FSQ, MASK_FSQ)
|
||||
DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S)
|
||||
DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S)
|
||||
DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S)
|
||||
|
|
@ -1068,6 +1193,10 @@ DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D)
|
|||
DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D)
|
||||
DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D)
|
||||
DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D)
|
||||
DECLARE_INSN(fmadd_q, MATCH_FMADD_Q, MASK_FMADD_Q)
|
||||
DECLARE_INSN(fmsub_q, MATCH_FMSUB_Q, MASK_FMSUB_Q)
|
||||
DECLARE_INSN(fnmsub_q, MATCH_FNMSUB_Q, MASK_FNMSUB_Q)
|
||||
DECLARE_INSN(fnmadd_q, MATCH_FNMADD_Q, MASK_FNMADD_Q)
|
||||
DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP)
|
||||
DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP)
|
||||
DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR)
|
||||
|
|
@ -1174,23 +1303,45 @@ DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31)
|
|||
DECLARE_CSR(sstatus, CSR_SSTATUS)
|
||||
DECLARE_CSR(sie, CSR_SIE)
|
||||
DECLARE_CSR(stvec, CSR_STVEC)
|
||||
DECLARE_CSR(scounteren, CSR_SCOUNTEREN)
|
||||
DECLARE_CSR(sscratch, CSR_SSCRATCH)
|
||||
DECLARE_CSR(sepc, CSR_SEPC)
|
||||
DECLARE_CSR(scause, CSR_SCAUSE)
|
||||
DECLARE_CSR(sbadaddr, CSR_SBADADDR)
|
||||
DECLARE_CSR(stval, CSR_STVAL)
|
||||
DECLARE_CSR(sip, CSR_SIP)
|
||||
DECLARE_CSR(sptbr, CSR_SPTBR)
|
||||
DECLARE_CSR(satp, CSR_SATP)
|
||||
DECLARE_CSR(mstatus, CSR_MSTATUS)
|
||||
DECLARE_CSR(misa, CSR_MISA)
|
||||
DECLARE_CSR(medeleg, CSR_MEDELEG)
|
||||
DECLARE_CSR(mideleg, CSR_MIDELEG)
|
||||
DECLARE_CSR(mie, CSR_MIE)
|
||||
DECLARE_CSR(mtvec, CSR_MTVEC)
|
||||
DECLARE_CSR(mcounteren, CSR_MCOUNTEREN)
|
||||
DECLARE_CSR(mscratch, CSR_MSCRATCH)
|
||||
DECLARE_CSR(mepc, CSR_MEPC)
|
||||
DECLARE_CSR(mcause, CSR_MCAUSE)
|
||||
DECLARE_CSR(mbadaddr, CSR_MBADADDR)
|
||||
DECLARE_CSR(mtval, CSR_MTVAL)
|
||||
DECLARE_CSR(mip, CSR_MIP)
|
||||
DECLARE_CSR(pmpcfg0, CSR_PMPCFG0)
|
||||
DECLARE_CSR(pmpcfg1, CSR_PMPCFG1)
|
||||
DECLARE_CSR(pmpcfg2, CSR_PMPCFG2)
|
||||
DECLARE_CSR(pmpcfg3, CSR_PMPCFG3)
|
||||
DECLARE_CSR(pmpaddr0, CSR_PMPADDR0)
|
||||
DECLARE_CSR(pmpaddr1, CSR_PMPADDR1)
|
||||
DECLARE_CSR(pmpaddr2, CSR_PMPADDR2)
|
||||
DECLARE_CSR(pmpaddr3, CSR_PMPADDR3)
|
||||
DECLARE_CSR(pmpaddr4, CSR_PMPADDR4)
|
||||
DECLARE_CSR(pmpaddr5, CSR_PMPADDR5)
|
||||
DECLARE_CSR(pmpaddr6, CSR_PMPADDR6)
|
||||
DECLARE_CSR(pmpaddr7, CSR_PMPADDR7)
|
||||
DECLARE_CSR(pmpaddr8, CSR_PMPADDR8)
|
||||
DECLARE_CSR(pmpaddr9, CSR_PMPADDR9)
|
||||
DECLARE_CSR(pmpaddr10, CSR_PMPADDR10)
|
||||
DECLARE_CSR(pmpaddr11, CSR_PMPADDR11)
|
||||
DECLARE_CSR(pmpaddr12, CSR_PMPADDR12)
|
||||
DECLARE_CSR(pmpaddr13, CSR_PMPADDR13)
|
||||
DECLARE_CSR(pmpaddr14, CSR_PMPADDR14)
|
||||
DECLARE_CSR(pmpaddr15, CSR_PMPADDR15)
|
||||
DECLARE_CSR(tselect, CSR_TSELECT)
|
||||
DECLARE_CSR(tdata1, CSR_TDATA1)
|
||||
DECLARE_CSR(tdata2, CSR_TDATA2)
|
||||
|
|
@ -1229,8 +1380,6 @@ DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28)
|
|||
DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29)
|
||||
DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30)
|
||||
DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31)
|
||||
DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN)
|
||||
DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN)
|
||||
DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3)
|
||||
DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4)
|
||||
DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5)
|
||||
|
|
@ -1327,20 +1476,21 @@ DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H)
|
|||
DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H)
|
||||
DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H)
|
||||
DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H)
|
||||
|
||||
#endif
|
||||
#ifdef DECLARE_CAUSE
|
||||
DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH)
|
||||
DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH)
|
||||
DECLARE_CAUSE("fetch access", CAUSE_FETCH_ACCESS)
|
||||
DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION)
|
||||
DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT)
|
||||
DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD)
|
||||
DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD)
|
||||
DECLARE_CAUSE("load access", CAUSE_LOAD_ACCESS)
|
||||
DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE)
|
||||
DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE)
|
||||
DECLARE_CAUSE("store access", CAUSE_STORE_ACCESS)
|
||||
DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL)
|
||||
DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL)
|
||||
DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL)
|
||||
DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL)
|
||||
DECLARE_CAUSE("fetch page fault", CAUSE_FETCH_PAGE_FAULT)
|
||||
DECLARE_CAUSE("load page fault", CAUSE_LOAD_PAGE_FAULT)
|
||||
DECLARE_CAUSE("store page fault", CAUSE_STORE_PAGE_FAULT)
|
||||
#endif
|
||||
|
||||
#endif /* RISCV_CSR_ENCODING_H */
|
||||
|
|
|
|||
|
|
@ -14,6 +14,7 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <arch/encoding.h>
|
||||
#include <arch/exception.h>
|
||||
#include <console/console.h>
|
||||
#include <string.h>
|
||||
|
|
@ -33,8 +34,12 @@ static const char *const exception_names[] = {
|
|||
"Store access fault",
|
||||
"Environment call from U-mode",
|
||||
"Environment call from S-mode",
|
||||
"Environment call from H-mode",
|
||||
"Environment call from M-mode"
|
||||
"Reserved (10)",
|
||||
"Environment call from M-mode",
|
||||
"Instruction page fault",
|
||||
"Load page fault",
|
||||
"Reserved (14)",
|
||||
"Store page fault",
|
||||
};
|
||||
|
||||
static const char *mstatus_to_previous_mode(uintptr_t ms)
|
||||
|
|
@ -119,7 +124,7 @@ static void interrupt_handler(trapframe *tf)
|
|||
// at present, as we only search for
|
||||
// "core{0{0{timecmp" above.
|
||||
ssie = read_csr(sie);
|
||||
if (!(ssie & SIE_STIE))
|
||||
if (!(ssie & SIP_STIP))
|
||||
break;
|
||||
|
||||
if (!timecmp)
|
||||
|
|
@ -149,11 +154,11 @@ void trap_handler(trapframe *tf)
|
|||
|
||||
switch(tf->cause) {
|
||||
case CAUSE_MISALIGNED_FETCH:
|
||||
case CAUSE_FAULT_FETCH:
|
||||
case CAUSE_FETCH_ACCESS:
|
||||
case CAUSE_ILLEGAL_INSTRUCTION:
|
||||
case CAUSE_BREAKPOINT:
|
||||
case CAUSE_FAULT_LOAD:
|
||||
case CAUSE_FAULT_STORE:
|
||||
case CAUSE_LOAD_ACCESS:
|
||||
case CAUSE_STORE_ACCESS:
|
||||
case CAUSE_USER_ECALL:
|
||||
case CAUSE_SUPERVISOR_ECALL:
|
||||
case CAUSE_HYPERVISOR_ECALL:
|
||||
|
|
|
|||
|
|
@ -26,11 +26,11 @@
|
|||
* the spec so for now we enumerate and set them all. */
|
||||
static int delegate = 0
|
||||
| (1 << CAUSE_MISALIGNED_FETCH)
|
||||
| (1 << CAUSE_FAULT_FETCH)
|
||||
| (1 << CAUSE_FETCH_ACCESS)
|
||||
| (1 << CAUSE_ILLEGAL_INSTRUCTION)
|
||||
| (1 << CAUSE_BREAKPOINT)
|
||||
| (1 << CAUSE_FAULT_LOAD)
|
||||
| (1 << CAUSE_FAULT_STORE)
|
||||
| (1 << CAUSE_LOAD_ACCESS)
|
||||
| (1 << CAUSE_STORE_ACCESS)
|
||||
| (1 << CAUSE_USER_ECALL)
|
||||
;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue