GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Trivial. Re-indent the code. 

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6301 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2011-01-27 03:31:50 +00:00 committed by Zheng Bao
parent 066cbe0cb7
commit a5c949eff2
4 changed files with 25 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
src/southbridge/amd/sb700/early_setup.c
View File

@ -41,7 +41,8 @@ static u8 pmio_read(u8 reg)
return inb(PM_INDEX + 1); return inb(PM_INDEX + 1);
} }
static void sb700_acpi_init(void) { static void sb700_acpi_init(void)
{
pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF); pmio_write(0x20, ACPI_PM_EVT_BLK & 0xFF);
pmio_write(0x21, ACPI_PM_EVT_BLK >> 8); pmio_write(0x21, ACPI_PM_EVT_BLK >> 8);
pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF); pmio_write(0x22, ACPI_PM1_CNT_BLK & 0xFF);
@ -624,7 +625,8 @@ static int smbus_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address); return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
} }
int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
{
int i; int i;
printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
@ -637,7 +639,8 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
return nvram_pos; return nvram_pos;
} }
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
{
u32 data = *old_dword; u32 data = *old_dword;
int i; int i;
for (i = 0; i<size; i++) { for (i = 0; i<size; i++) {
@ -653,7 +656,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
} }
#if CONFIG_HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
static int acpi_is_wakeup_early(void) { static int acpi_is_wakeup_early(void)
{
u16 tmp; u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK); tmp = inw(ACPI_PM1_CNT_BLK);
printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
@ -661,7 +665,8 @@ static int acpi_is_wakeup_early(void) {
} }
#endif #endif
struct cbmem_entry *get_cbmem_toc(void) { struct cbmem_entry *get_cbmem_toc(void)
{
uint32_t xdata = 0; uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi; int xnvram_pos = 0xfc, xi;
for (xi = 0; xi<4; xi++) { for (xi = 0; xi<4; xi++) {

3
src/southbridge/amd/sb700/lpc.c
View File

@ -77,7 +77,8 @@ static void lpc_init(device_t dev)
#endif #endif
} }
void set_cbmem_toc(struct cbmem_entry *toc) { void set_cbmem_toc(struct cbmem_entry *toc)
{
u32 dword = (u32) toc; u32 dword = (u32) toc;
int nvram_pos = 0xfc, i; int nvram_pos = 0xfc, i;
for (i = 0; i<4; i++) { for (i = 0; i<4; i++) {

4
src/southbridge/amd/sb700/sata.c
View File

@ -54,8 +54,8 @@ static int sata_drive_detect(int portnum, u16 iobar)
} }
/* This function can be overloaded in mainboard.c */ /* This function can be overloaded in mainboard.c */
void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev)
void __attribute__((weak)) sb700_setup_sata_phys(struct device *dev) { {
/* RPR7.6.1 Program the PHY Global Control to 0x2C00 */ /* RPR7.6.1 Program the PHY Global Control to 0x2C00 */
pci_write_config16(dev, 0x86, 0x2c00); pci_write_config16(dev, 0x86, 0x2c00);

15
src/southbridge/amd/sb800/early_setup.c
View File

@ -41,7 +41,8 @@ static u8 pmio_read(u8 reg)
return inb(PM_INDEX + 1); return inb(PM_INDEX + 1);
} }
static void sb800_acpi_init(void) { static void sb800_acpi_init(void)
{
pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF); pmio_write(0x60, ACPI_PM_EVT_BLK & 0xFF);
pmio_write(0x61, ACPI_PM_EVT_BLK >> 8); pmio_write(0x61, ACPI_PM_EVT_BLK >> 8);
pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF); pmio_write(0x62, ACPI_PM1_CNT_BLK & 0xFF);
@ -652,7 +653,8 @@ static int smbus_read_byte(u32 device, u32 address)
return do_smbus_read_byte(SMBUS_IO_BASE, device, address); return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
} }
int s3_save_nvram_early(u32 dword, int size, int nvram_pos) { int s3_save_nvram_early(u32 dword, int size, int nvram_pos)
{
int i; int i;
printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos);
@ -665,7 +667,8 @@ int s3_save_nvram_early(u32 dword, int size, int nvram_pos) {
return nvram_pos; return nvram_pos;
} }
int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) { int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos)
{
u32 data = *old_dword; u32 data = *old_dword;
int i; int i;
for (i = 0; i<size; i++) { for (i = 0; i<size; i++) {
@ -681,7 +684,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) {
} }
#if CONFIG_HAVE_ACPI_RESUME == 1 #if CONFIG_HAVE_ACPI_RESUME == 1
static int acpi_is_wakeup_early(void) { static int acpi_is_wakeup_early(void)
{
u16 tmp; u16 tmp;
tmp = inw(ACPI_PM1_CNT_BLK); tmp = inw(ACPI_PM1_CNT_BLK);
printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp); printk(BIOS_DEBUG, "IN TEST WAKEUP %x\n", tmp);
@ -689,7 +693,8 @@ static int acpi_is_wakeup_early(void) {
} }
#endif #endif
struct cbmem_entry *get_cbmem_toc(void) { struct cbmem_entry *get_cbmem_toc(void)
{
uint32_t xdata = 0; uint32_t xdata = 0;
int xnvram_pos = 0xfc, xi; int xnvram_pos = 0xfc, xi;
for (xi = 0; xi<4; xi++) { for (xi = 0; xi<4; xi++) {