soc/mediatek: Move SPMI device table to SoC folder

The SPMI devices on MT8188 are different from previous SoCs, so we
move them to SoC folder.

We also move SoC-specific definitions to soc/pmif.h.

TEST=build pass
BUG=b:233720142

Signed-off-by: Hui Liu <hui.liu@mediatek.corp-partner.google.com>
Change-Id: I666c2a8222a2bd8cd460e2225a7ae48b001da9d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65757
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Hui Liu 2022-07-05 14:53:22 +08:00 committed by Felix Held
parent 1ad10ee7a5
commit a5c9682633
7 changed files with 51 additions and 21 deletions

View File

@ -5,14 +5,11 @@
#include <soc/addressmap.h> #include <soc/addressmap.h>
#include <soc/pmif.h> #include <soc/pmif.h>
#include <soc/spmi.h>
#define DEFAULT_VALUE_READ_TEST (0x5a) #define DEFAULT_VALUE_READ_TEST (0x5a)
#define DEFAULT_VALUE_WRITE_TEST (0xa5) #define DEFAULT_VALUE_WRITE_TEST (0xa5)
/* indicate which number SW channel start, by project */
#define PMIF_SPMI_SW_CHAN BIT(6)
#define PMIF_SPMI_INF 0x2F7
struct mtk_rgu_regs { struct mtk_rgu_regs {
u32 reserved[36]; u32 reserved[36];
u32 wdt_swsysrst2; u32 wdt_swsysrst2;
@ -82,6 +79,9 @@ enum {
#define MT6315_DEFAULT_VALUE_READ 0x15 #define MT6315_DEFAULT_VALUE_READ 0x15
extern const struct spmi_device spmi_dev[];
extern const size_t spmi_dev_cnt;
int pmif_spmi_init(struct pmif *arb); int pmif_spmi_init(struct pmif *arb);
int spmi_config_master(void); int spmi_config_master(void);
void pmif_spmi_iocfg(void); void pmif_spmi_iocfg(void);

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@ -4,6 +4,7 @@
#include <delay.h> #include <delay.h>
#include <soc/mt6315.h> #include <soc/mt6315.h>
#include <soc/pmif.h> #include <soc/pmif.h>
#include <soc/pmif_spmi.h>
static struct pmif *pmif_arb = NULL; static struct pmif *pmif_arb = NULL;
@ -95,8 +96,12 @@ static void init_pmif_arb(void)
void mt6315_init(void) void mt6315_init(void)
{ {
size_t i;
init_pmif_arb(); init_pmif_arb();
mt6315_wdt_enable(MT6315_CPU);
mt6315_wdt_enable(MT6315_GPU); for (i = 0; i < spmi_dev_cnt; i++)
mt6315_wdt_enable(spmi_dev[i].slvid);
mt6315_init_setting(); mt6315_init_setting();
} }

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@ -25,19 +25,6 @@ DEFINE_BIT(SPI_EINT_MODE_GATING_EN, 13)
DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0) DEFINE_BITFIELD(SPM_SLEEP_REQ_SEL, 1, 0)
DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9) DEFINE_BITFIELD(SCP_SLEEP_REQ_SEL, 10, 9)
static const struct spmi_device spmi_dev[] = {
{
.slvid = SPMI_SLAVE_6,
.type = BUCK_CPU,
.type_id = BUCK_CPU_ID,
},
{
.slvid = SPMI_SLAVE_7,
.type = BUCK_GPU,
.type_id = BUCK_GPU_ID,
},
};
static int spmi_read_check(struct pmif *pmif_arb, int slvid) static int spmi_read_check(struct pmif *pmif_arb, int slvid)
{ {
u32 rdata = 0; u32 rdata = 0;
@ -88,7 +75,7 @@ static int spmi_cali_rd_clock_polarity(struct pmif *pmif_arb, const struct spmi_
static int spmi_mst_init(struct pmif *pmif_arb) static int spmi_mst_init(struct pmif *pmif_arb)
{ {
int i; size_t i;
if (!pmif_arb) { if (!pmif_arb) {
printk(BIOS_ERR, "%s: null pointer for pmif dev.\n", __func__); printk(BIOS_ERR, "%s: null pointer for pmif dev.\n", __func__);
@ -98,7 +85,7 @@ static int spmi_mst_init(struct pmif *pmif_arb)
pmif_spmi_iocfg(); pmif_spmi_iocfg();
spmi_config_master(); spmi_config_master();
for (i = 0; i < ARRAY_SIZE(spmi_dev); i++) for (i = 0; i < spmi_dev_cnt; i++)
spmi_cali_rd_clock_polarity(pmif_arb, &spmi_dev[i]); spmi_cali_rd_clock_polarity(pmif_arb, &spmi_dev[i]);
return 0; return 0;

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@ -7,6 +7,10 @@
#include <soc/pmif_common.h> #include <soc/pmif_common.h>
#include <types.h> #include <types.h>
/* indicate which number SW channel start, by project */
#define PMIF_SPMI_SW_CHAN BIT(6)
#define PMIF_SPMI_INF 0x2F7
struct mtk_pmif_regs { struct mtk_pmif_regs {
u32 init_done; u32 init_done;
u32 reserved1[5]; u32 reserved1[5];

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@ -21,6 +21,21 @@ DEFINE_BIT(PDN_SPMI_MST, 15)
/* TOPCKGEN, CLK_CFG_UPDATE2 */ /* TOPCKGEN, CLK_CFG_UPDATE2 */
DEFINE_BIT(SPMI_MST_CK_UPDATE, 30) DEFINE_BIT(SPMI_MST_CK_UPDATE, 30)
const struct spmi_device spmi_dev[] = {
{
.slvid = SPMI_SLAVE_6,
.type = BUCK_CPU,
.type_id = BUCK_CPU_ID,
},
{
.slvid = SPMI_SLAVE_7,
.type = BUCK_GPU,
.type_id = BUCK_GPU_ID,
},
};
const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
int spmi_config_master(void) int spmi_config_master(void)
{ {
/* Software reset */ /* Software reset */

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@ -7,6 +7,10 @@
#include <soc/pmif_common.h> #include <soc/pmif_common.h>
#include <types.h> #include <types.h>
/* indicate which number SW channel start, by project */
#define PMIF_SPMI_SW_CHAN BIT(6)
#define PMIF_SPMI_INF 0x2F7
struct mtk_pmif_regs { struct mtk_pmif_regs {
u32 init_done; u32 init_done;
u32 reserved1[5]; u32 reserved1[5];

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@ -30,6 +30,21 @@ DEFINE_BIT(PDN_SPMI_MST, 15)
/* TOPCKGEN, CLK_CFG_UPDATE2 */ /* TOPCKGEN, CLK_CFG_UPDATE2 */
DEFINE_BIT(SPMI_MST_CK_UPDATE, 5) DEFINE_BIT(SPMI_MST_CK_UPDATE, 5)
const struct spmi_device spmi_dev[] = {
{
.slvid = SPMI_SLAVE_6,
.type = BUCK_CPU,
.type_id = BUCK_CPU_ID,
},
{
.slvid = SPMI_SLAVE_7,
.type = BUCK_GPU,
.type_id = BUCK_GPU_ID,
},
};
const size_t spmi_dev_cnt = ARRAY_SIZE(spmi_dev);
int spmi_config_master(void) int spmi_config_master(void)
{ {
/* Software reset */ /* Software reset */