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Prepare for next patches (Improving BKDG implementation of P-states, 

CPU and northbridge frequency and voltage
handling for Fam 10 in SVI mode).

No change of behaviour intended.

Refactor FAM10 fidvid . prep_fid_change was already long and it'd
get longer with forthcoming patches. We now take apart F3xD4,
Clock Power/Timing Control 0 to its own function.

Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat>
Acked-by: Marc Jones <marcj303@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6388 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Xavi Drudis Ferran 2011-02-27 23:45:34 +00:00 committed by Marc Jones
parent d729459621
commit a5cbd25e48
1 changed files with 53 additions and 46 deletions
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49
src/cpu/amd/model_10xxx/fidvid.c
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@ -179,27 +179,11 @@ static void recalculateVsSlamTimeSettingOnCorePre(device_t dev)
pci_write_config32(dev, 0xd8, dtemp); pci_write_config32(dev, 0xd8, dtemp);
} }
static void prep_fid_change(void) static void config_clk_power_ctrl_reg0(int node) {
{ u32 dword;
u32 dword, dtemp; device_t dev = NODE_PCI(node, 3);
u32 nodes;
device_t dev;
int i;
/* This needs to be run before any Pstate changes are requested */
nodes = get_nodes();
for (i = 0; i < nodes; i++) {
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i, 3);
setVSRamp(dev);
/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);
/* Program fields in Clock Power/Control register0 (F3xD4) */ /* Program fields in Clock Power/Control register0 (F3xD4) */
/* set F3xD4 Clock Power/Timing Control 0 Register /* set F3xD4 Clock Power/Timing Control 0 Register
* NbClkDidApplyAll=1b * NbClkDidApplyAll=1b
* NbClkDid=100b * NbClkDid=100b
@ -227,7 +211,7 @@ static void prep_fid_change(void)
3 cores - 133nS -> 100nS - 0011b 3 cores - 133nS -> 100nS - 0011b
4 cores - 100nS - 0011b 4 cores - 100nS - 0011b
*/ */
switch (get_core_num_in_bsp(i)) { switch (get_core_num_in_bsp(node)) {
case 0: case 0:
dword |= PW_STP_UP400 | PW_STP_DN400; dword |= PW_STP_UP400 | PW_STP_DN400;
break; break;
@ -245,6 +229,29 @@ static void prep_fid_change(void)
dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK; dword |= NB_CLKDID_ALL | NB_CLKDID | LNK_PLL_LOCK;
pci_write_config32(dev, 0xd4, dword); pci_write_config32(dev, 0xd4, dword);
} }
}
static void prep_fid_change(void)
{
u32 dword, dtemp;
u32 nodes;
device_t dev;
int i;
/* This needs to be run before any Pstate changes are requested */
nodes = get_nodes();
for (i = 0; i < nodes; i++) {
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i, 3);
setVSRamp(dev);
/* BKDG r31116 2010-04-22 2.4.1.7 step b F3xD8[VSSlamTime] */
/* Figure out the value for VsSlamTime and program it */
recalculateVsSlamTimeSettingOnCorePre(dev);
config_clk_power_ctrl_reg0(i);
/* check PVI/SVI */ /* check PVI/SVI */
dword = pci_read_config32(dev, 0xA0); dword = pci_read_config32(dev, 0xA0);