soc/amd: move warm reset flag function prototypes to common code

Even though the implementation is different on Stoneyridge compared to
Picasso and Cezanne, the function prototypes are identical, so move them
to the AMD SoC common reset header file.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8d3a3a9ea568ea18658c49612efabdbe36d5f957
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51395
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>

src/soc/amd/cezanne/cpu.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <console/console.h>
 #include <cpu/amd/microcode.h>
@@ -12,7 +13,6 @@
 #include <device/device.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
-#include <soc/reset.h>
 
 /* MP and SMM loading initialization */
 

src/soc/amd/cezanne/include/soc/reset.h

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_CEZANNE_RESET_H
-#define AMD_CEZANNE_RESET_H
-
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* AMD_CEZANNE_RESET_H */

src/soc/amd/cezanne/reset.c

@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <reset.h>
-#include <soc/reset.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>

src/soc/amd/common/block/include/amdblocks/reset.h

@@ -9,6 +9,8 @@
 
 void do_warm_reset(void);
 void do_cold_reset(void);
+void set_warm_reset_flag(void);
+int is_warm_reset(void);
 
 static inline __noreturn void warm_reset(void)
 {

src/soc/amd/picasso/cpu.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <amdblocks/cpu.h>
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
@@ -12,7 +13,6 @@
 #include <device/pci_ops.h>
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
-#include <soc/reset.h>
 #include <soc/smi.h>
 #include <soc/iomap.h>
 #include <console/console.h>

src/soc/amd/picasso/include/soc/reset.h

@@ -1,9 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef AMD_PICASSO_RESET_H
-#define AMD_PICASSO_RESET_H
-
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
-
-#endif /* AMD_PICASSO_RESET_H */

src/soc/amd/picasso/mca.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/reset.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>

src/soc/amd/picasso/reset.c

@@ -3,7 +3,6 @@
 #include <arch/io.h>
 #include <cf9_reset.h>
 #include <reset.h>
-#include <soc/reset.h>
 #include <soc/southbridge.h>
 #include <amdblocks/acpimmio.h>
 #include <amdblocks/reset.h>

src/soc/amd/stoneyridge/cpu.c

@@ -1,5 +1,6 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <amdblocks/smm.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>

src/soc/amd/stoneyridge/include/soc/northbridge.h

@@ -86,7 +86,5 @@
 void domain_enable_resources(struct device *dev);
 void domain_read_resources(struct device *dev);
 void fam15_finalize(void *chip_info);
-void set_warm_reset_flag(void);
-int is_warm_reset(void);
 
 #endif /* AMD_STONEYRIDGE_NORTHBRIDGE_H */

src/soc/amd/stoneyridge/mca.c

@@ -1,9 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <amdblocks/reset.h>
 #include <cpu/x86/msr.h>
 #include <acpi/acpi.h>
 #include <soc/cpu.h>
-#include <soc/northbridge.h>
 #include <console/console.h>
 #include <arch/bert_storage.h>
 #include <cper.h>