braswell: Tristate CFIO 139 and CFIO 140

CFIO 139 and CFIO 140 are consuming ~5 during stanndby. The reason
for this leakage is internally it is configured to 1K PU. So there
is leakage of ~2mW in standby. Total impact ~2.5 mw in Srandby.

Configure these CFIOs as tristate for ~5mW power saving at platform
level.

BRANCH=none
TEST=PnP Team to verify that the CFIO's are tri-stated.

Change-Id: I6d78d2ccc08167b2cd6fc3405cfcb5c69a77d4b8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f11eb98cb36c504dfebe6f0fa53e9af120d21f24
Original-Change-Id: Ib309ad0c6abffa4515fdf2a2f2d9174fad7f8e8d
Original-Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Original-Signed-off-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292863
Original-Commit-Ready: Rajmohan Mani <rajmohan.mani@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11556
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/braswell/include/soc/gpio.h

@@ -110,6 +110,8 @@
 #define MMC1_D7_MMIO_OFFSET		GPIO_OFFSET(68)
 #define HV_DDI2_DDC_SDA_MMIO_OFFSET	GPIO_OFFSET(62)
 #define HV_DDI2_DDC_SCL_MMIO_OFFSET	GPIO_OFFSET(67)
+#define CFIO_139_MMIO_OFFSET		GPIO_OFFSET(64)
+#define CFIO_140_MMIO_OFFSET		GPIO_OFFSET(67)
 
 /* GPIO Security registers offset */
 #define GPIO_READ_ACCESS_POLICY_REG	0x0000

src/soc/intel/braswell/smihandler.c

@@ -127,6 +127,12 @@ static void tristate_gpios(uint32_t val)
 			HV_DDI2_DDC_SDA_MMIO_OFFSET, val);
 	write32((void *)COMMUNITY_GPNORTH_BASE +
 			HV_DDI2_DDC_SCL_MMIO_OFFSET, val);
+
+	/* Tri-state CFIO 139 and 140 */
+	write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
+			CFIO_139_MMIO_OFFSET, val);
+	write32((void *)COMMUNITY_GPSOUTHWEST_BASE +
+			CFIO_140_MMIO_OFFSET, val);
 }