htx card on io apic on htx slot of dk8_htx

Signed-off-by: Yinghai Lu <yinghai.lu@amd.com>
Acked-by: Yinghai Lu <yinghai.lu@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2533 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/mainboard/iwill/dk8_htx/Config.lb

@@ -119,6 +119,13 @@ if HAVE_ACPI_TABLES
                         action  "mv pci4.hex ssdt4.c"
             end
             object ./ssdt4.o
+            makerule ssdt5.c
+                        depends "$(MAINBOARD)/dx/pci5.asl"
+                        action  "iasl -tc $(MAINBOARD)/dx/pci5.asl"
+                        action  "perl -pi -e 's/AmlCode/AmlCode_ssdt5/g' pci5.hex"
+                        action  "mv pci5.hex ssdt5.c"
+            end
+            object ./ssdt5.o
         end
 end
 

src/mainboard/iwill/dk8_htx/acpi_tables.c

@@ -44,6 +44,7 @@ extern unsigned char AmlCode_ssdt[];
 extern unsigned char AmlCode_ssdt2[];
 extern unsigned char AmlCode_ssdt3[];
 extern unsigned char AmlCode_ssdt4[];
+extern unsigned char AmlCode_ssdt5[];
 #endif
 
 #define IO_APIC_ADDR	0xfec00000UL
@@ -286,7 +287,9 @@ unsigned long write_acpi_tables(unsigned long start)
                         p = AmlCode_ssdt4;
                         break;
                 default:
-                        continue;
+			//HTX no io apic
+                        p = AmlCode_ssdt5;
+			break;
                 }
                 current += ((acpi_header_t *)p)->length;
                 memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length);

src/mainboard/iwill/dk8_htx/dx/htx_no_ioapic.asl

@@ -0,0 +1,20 @@
+/*
+ * Copyright 2006 AMD
+ */
+		
+            Device (HTXA)
+            {
+                /*  HTX */
+                Method (_ADR, 0, NotSerialized)
+                {
+                        Return (DADD(GHCD(HCIN, 0), 0x00000000))
+                }
+
+                Method (_PRW, 0, NotSerialized)
+                {
+                    If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+                    Else { Return (Package (0x02) { 0x29, 0x01 }) }
+                }
+
+            }
+

src/mainboard/iwill/dk8_htx/dx/pci5.asl

@@ -0,0 +1,68 @@
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT5.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+    Scope (_SB)
+    {
+	External (DADD, MethodObj)
+	External (GHCE, MethodObj)
+	External (GHCN, MethodObj)
+	External (GHCL, MethodObj)
+	External (GHCD, MethodObj)
+	External (GNUS, MethodObj)
+	External (GIOR, MethodObj)
+	External (GMEM, MethodObj)
+	External (GWBN, MethodObj)
+	External (GBUS, MethodObj)
+
+	External (PICF)
+
+	External (\_SB.PCI0.LNKA, DeviceObj)
+	External (\_SB.PCI0.LNKB, DeviceObj)
+	External (\_SB.PCI0.LNKC, DeviceObj)
+	External (\_SB.PCI0.LNKD, DeviceObj)
+
+        Device (PCIX)
+        {
+
+	    // BUS ? Second HT Chain
+	    Name (HCIN, 0xcc)  // HC2 0x01
+            
+	    Name (_UID,  0xdd)  // HC 0x03
+
+	    Name (_HID, "PNP0A03") 
+
+            Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+	    {
+		Return (DADD(GHCN(HCIN), 0x00000000))
+	    }
+	
+            Method (_BBN, 0, NotSerialized)
+            {
+                Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+            }
+
+            Method (_STA, 0, NotSerialized)
+            {
+                Return (\_SB.GHCE(HCIN)) 
+            }
+
+            Method (_CRS, 0, NotSerialized)
+            {
+                Name (BUF0, ResourceTemplate () { })
+		Store( GHCN(HCIN), Local4)
+		Store( GHCL(HCIN), Local5)
+
+                Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+                Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+                Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+                Return (Local3)
+            }
+
+	    Include ("pci5_hc.asl")
+        }
+    }
+
+}
+

src/mainboard/iwill/dk8_htx/dx/pci5_hc.asl

@@ -0,0 +1 @@
+	Include ("htx_no_ioapic.asl")