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mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2 

This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.

BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.

Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
V Sowmya 2020-12-02 12:00:48 +05:30 committed by Subrata Banik
parent 2082196e95
commit a6051440e2
1 changed files with 9 additions and 1 deletions
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10
src/mainboard/intel/adlrvp/variants/adlrvp_p_ext_ec/overridetree.cb
View File

@ -3,9 +3,10 @@ chip soc/intel/alderlake
device domain 0 on device domain 0 on
device pci 1f.0 on device pci 1f.0 on
chip ec/google/chromeec chip ec/google/chromeec
device pnp 0c09.0 on end
use conn0 as mux_conn[0] use conn0 as mux_conn[0]
use conn1 as mux_conn[1] use conn1 as mux_conn[1]
use conn2 as mux_conn[2]
device pnp 0c09.0 on end
end end
end # eSPI end # eSPI
device pci 1f.2 hidden device pci 1f.2 hidden
@ -27,6 +28,13 @@ chip soc/intel/alderlake
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 1 alias conn1 on end device generic 1 alias conn1 on end
end end
chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "3"
register "usb3_port_number" = "3"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
device generic 2 alias conn2 on end
end
end end
end end
end # PMC end # PMC