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arm64: provide icache_invalidate_all() 

In order to not duplicate the instruction cache invalidation
sequence provide a common routine to perform the necessary
actions. Also, use it in the appropriate places.

BUG=None
BRANCH=None
TEST=Built on ryu.

Change-Id: I29ea2371d034c0193949ebb10beb840e7215281a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d5ab28b5d73c03adcdc0fd4e530b39a7a8989dae
Original-Change-Id: I8d5f648c995534294e3222e2dc2091a075dd6beb
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/260949
Original-Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Original-Commit-Queue: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: http://review.coreboot.org/9871
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Aaron Durbin 2015-03-18 17:02:28 -05:00 committed by Patrick Georgi
parent b41914952d
commit a612fc1202
3 changed files with 15 additions and 3 deletions
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4
src/arch/arm64/armv8/cache.c
View File

@ -144,7 +144,5 @@ void dcache_mmu_enable(void)
void cache_sync_instructions(void) void cache_sync_instructions(void)
{ {
flush_dcache_all(); /* includes trailing DSB (in assembly) */ flush_dcache_all(); /* includes trailing DSB (in assembly) */
iciallu(); /* includes BPIALLU (architecturally) */ icache_invalidate_all(); /* includdes leading DSB and trailing ISB. */
dsb();
isb();
} }

3
src/arch/arm64/armv8/secmon_loader.c
View File

@ -22,6 +22,7 @@
* and parameter location for the rmodule. * and parameter location for the rmodule.
*/ */
#include <arch/cache.h>
#include <arch/lib_helpers.h> #include <arch/lib_helpers.h>
#include <arch/secmon.h> #include <arch/secmon.h>
#include <arch/spintable.h> #include <arch/spintable.h>
@ -106,6 +107,8 @@ static void secmon_start(void *arg)
scr |= SCR_NS; scr |= SCR_NS;
raw_write_scr_el3(scr); raw_write_scr_el3(scr);
/* Invalidate instruction cache. Necessary for non-BSP. */
icache_invalidate_all();
entry(p); entry(p);
} }

11
src/arch/arm64/include/armv8/arch/cache.h
View File

@ -86,4 +86,15 @@ void cache_sync_instructions(void);
/* tlb invalidate all */ /* tlb invalidate all */
void tlb_invalidate_all(void); void tlb_invalidate_all(void);
/* Invalidate all of the instruction cache for PE to PoU. */
static inline void icache_invalidate_all(void)
{
__asm__ __volatile__(
"dsb sy\n\t"
"ic iallu\n\t"
"dsb sy\n\t"
"isb\n\t"
: : : "memory");
}
#endif /* ARM_ARM64_CACHE_H */ #endif /* ARM_ARM64_CACHE_H */