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intel: Drop obsolete comments on MTRR usage 

Problem with UMA region allocation was fixed when MTRRs changed to use
memrange implementation.

Change-Id: I420dac30de2836a91596d81f88bb45b46f248532
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/5719
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Kyösti Mälkki 2014-05-12 15:00:03 +03:00
parent a823f9b545
commit a6130fc8f9
4 changed files with 0 additions and 37 deletions
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4
src/include/device/device.h
View File

@ -211,10 +211,6 @@ void fixed_mem_resource(device_t dev, unsigned long index,
/* It is the caller's responsibility to adjust regions such that ram_resource()
* and mmio_resource() do not overlap.
*
* Current MTRR setup creates exclusive uncacheable holes for uma_resource()
* only and these are allowed to overlap any ram_resource(). This approach
* is used for all UMA except Intel Sandy/IvyBridge.
*/
#define ram_resource(dev, idx, basek, sizek) \
fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)

11
src/northbridge/intel/fsp_sandybridge/northbridge.c
View File

@ -102,17 +102,6 @@ static void add_fixed_resources(struct device *dev, int index)
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
/* Using uma_resource() here would fail as base & size cannot
* be used as-is for a single MTRR. This would cause excessive
* use of MTRRs.
*
* Use of mmio_resource() instead does not create UC holes by using
* MTRRs, but making these regions uncacheable is taken care of by
* making sure they do not overlap with any ram_resource().
*
* The resources can be changed to use separate mmio_resource()
* calls after MTRR code is able to merge them wisely.
*/
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {

11
src/northbridge/intel/nehalem/northbridge.c
View File

@ -134,17 +134,6 @@ static void mc_read_resources(device_t dev)
ram_resource(dev, 3, 0, 640);
ram_resource(dev, 4, 768, ((tseg_base >> 10) - 768));
/* Using uma_resource() here would fail as base & size cannot
* be used as-is for a single MTRR. This would cause excessive
* use of MTRRs.
*
* Use of mmio_resource() instead does not create UC holes by using
* MTRRs, but making these regions uncacheable is taken care of by
* making sure they do not overlap with any ram_resource().
*
* The resources can be changed to use separate mmio_resource()
* calls after MTRR code is able to merge them wisely.
*/
mmio_resource(dev, 5, tseg_base >> 10, CONFIG_SMM_TSEG_SIZE >> 10);
reg16 = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0, 0)), D0F0_GGC);

11
src/northbridge/intel/sandybridge/northbridge.c
View File

@ -100,17 +100,6 @@ static void add_fixed_resources(struct device *dev, int index)
struct resource *resource;
u32 pcie_config_base, pcie_config_size;
/* Using uma_resource() here would fail as base & size cannot
* be used as-is for a single MTRR. This would cause excessive
* use of MTRRs.
*
* Use of mmio_resource() instead does not create UC holes by using
* MTRRs, but making these regions uncacheable is taken care of by
* making sure they do not overlap with any ram_resource().
*
* The resources can be changed to use separate mmio_resource()
* calls after MTRR code is able to merge them wisely.
*/
mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10);
if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) {