mediatek/mt8173: pll: raising the CPU core frequency

Runs the LITTLE core at highest freqency to speed up the boot time.
Set Vproc to 1.125V and set the freqency to 1.6Ghz for backward
compatibility. (The highest frequency for the IC before E3 is 1.6Ghz.)

BRANCH=none
BUG=chrome-os-partner:47422
TEST=flash the bootloader and measure the boottime by cbmem result

Change-Id: Id0b906bf34ac534667eb6e8f576e30942ceb923e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5fc38548d158158f07cded8cfc8ea5a0a7952161
Original-Change-Id: I62af26c13d98211974243100c581abcb5408fd63
Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/324685
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13980
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/mainboard/google/oak/romstage.c

@@ -17,7 +17,7 @@
 #include <arch/exception.h>
 #include <arch/io.h>
 #include <arch/mmu.h>
-
+#include <boardid.h>
 #include <cbfs.h>
 #include <cbmem.h>
 #include <console/console.h>
@@ -25,14 +25,20 @@
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <symbols.h>
+#include <timer.h>
 #include <timestamp.h>
 
 #include <soc/emi.h>
 #include <soc/mmu_operations.h>
+#include <soc/mt6391.h>
+#include <soc/pll.h>
 #include <soc/rtc.h>
 
 void main(void)
 {
+	int stabilize_usec;
+	struct stopwatch sw;
+
 	timestamp_add_now(TS_START_ROMSTAGE);
 
 	/* init uart baudrate when pll on */
@@ -41,9 +47,23 @@ void main(void)
 
 	rtc_boot();
 
+	/* Raise CPU voltage to allow higher frequency */
+	stabilize_usec = mt6391_configure_ca53_voltage(1125000);
+
+	stopwatch_init_usecs_expire(&sw, stabilize_usec);
+
 	/* init memory */
 	mt_mem_init(get_sdram_config());
 
+	while (!stopwatch_expired(&sw))
+		;
+
+	/* Set to maximum frequency */
+	if (board_id() < 5)
+		mt_pll_raise_ca53_freq(1600 * MHz);
+	else
+		mt_pll_raise_ca53_freq(1700 * MHz);
+
 	mt8173_mmu_after_dram();
 
 	/* should be called after memory init */

src/soc/mediatek/mt8173/include/soc/mt6391.h

@@ -98,6 +98,7 @@ enum{
 	PMIC_RG_VCA15_CON9 = 0x0226,
 	PMIC_RG_VCA15_CON10 = 0x0228,
 	PMIC_RG_VCA15_CON11 = 0x022A,
+	PMIC_RG_VCA15_CON12 = 0x022C,
 	PMIC_RG_VCA15_CON18 = 0x0238,
 	PMIC_RG_VSRMCA15_CON5 = 0x0244,
 	PMIC_RG_VSRMCA15_CON6 = 0x0246,
@@ -291,6 +292,7 @@ enum ldo_voltage {
 /*
  * PMIC Exported Function
  */
+int mt6391_configure_ca53_voltage(int uv);
 void mt6391_configure_ldo(enum ldo_power ldo, enum ldo_voltage vsel);
 u32 mt6391_read(u16 reg, u32 mask, u32 shift);
 void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift);

src/soc/mediatek/mt8173/include/soc/pll.h

@@ -286,6 +286,7 @@ void mt_pll_post_init(void);
 void mt_pll_init(void);
 void mt_pll_set_aud_div(u32 rate);
 void mt_pll_enable_ssusb_clk(void);
+void mt_pll_raise_ca53_freq(u32 freq);
 void mt_mem_pll_set_clk_cfg(void);
 void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params);
 void mt_mem_pll_config_post(void);

src/soc/mediatek/mt8173/mt6391.c

@@ -59,6 +59,23 @@ void mt6391_write(u16 reg, u16 val, u32 mask, u32 shift)
 	return;
 }
 
+int mt6391_configure_ca53_voltage(int uv)
+{
+	/* target voltage = 700mv + 6.25mv * buck_val */
+	u16 buck_val = (uv - 700000) / 6250;
+	u16 current_val = mt6391_read(PMIC_RG_VCA15_CON12, 0x7f, 0x0);
+
+	assert(buck_val < (1 << 8));
+	mt6391_write(PMIC_RG_VCA15_CON9, buck_val, 0x7f, 0x0);
+	mt6391_write(PMIC_RG_VCA15_CON10, buck_val, 0x7f, 0x0);
+
+	/* For buck delay, default slew rate is 6.25mv/0.5us */
+	if (buck_val > current_val)
+		return ((buck_val - current_val) / 2) ;
+	else
+		return 0;
+}
+
 static void mt6391_configure_vcama(enum ldo_voltage vsel)
 {
 	/* 2'b00: 1.5V

src/soc/mediatek/mt8173/pll.c

@@ -467,8 +467,6 @@ void mt_pll_post_init(void)
 	clrbits_le32(&mt8173_infracfg->top_ckdiv1, 0x3ff);
 
 	/* select ARMPLL */
-	/* TODO: possibly raise ARMPLL frequency here */
-	/* NOTICE: raise Vproc voltage before raise ARMPLL frequency */
 	write32(&mt8173_infracfg->top_ckmuxsel, (1 << 2) | 1);
 }
 
@@ -506,6 +504,10 @@ void mt_pll_set_aud_div(u32 rate)
 	}
 }
 
+void mt_pll_raise_ca53_freq(u32 freq) {
+	pll_set_rate(&plls[APMIXED_ARMCA7PLL], freq); /* freq in Hz */
+}
+
 void mt_mem_pll_config_pre(const struct mt8173_sdram_params *sdram_params)
 {
 	u32 mpll_sdm_pcw_20_0 = 0xF13B1;