broadwell: Preparations for building
Updated Intel Broadwell for differences in the source based on the chromium tree. It is missing most of the recent updates on coreboot.org. - makefile changes for Elog and IDF tool - kconfig changes for ME, ucode, and other updates - update oprom flag - update timestamp mechanism - cbfs payload function is now generic Change-Id: I82bd0792e9dcf81085246873164de6600528d6fe Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/7939 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
This commit is contained in:
Marc Jones
parent
dffd892e47
commit
a6354a1aca
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@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
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select MMCONF_SUPPORT
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select MMCONF_SUPPORT_DEFAULT
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select RELOCATABLE_MODULES
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select RELOCATABLE_RAMSTAGE
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select REG_SCRIPT
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select PARALLEL_MP
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select PCIEXP_ASPM
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@ -39,6 +40,7 @@ config CPU_SPECIFIC_OPTIONS
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select SMP
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select SPI_FLASH
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select SSE2
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select SUPPORT_CPU_UCODE_IN_CBFS
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select TSC_CONSTANT_RATE
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select TSC_SYNC_MFENCE
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select UDELAY_TSC
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@ -56,9 +58,6 @@ config BOOTBLOCK_SOUTHBRIDGE_INIT
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string
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default "soc/intel/broadwell/bootblock/pch.c"
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config MICROCODE_INCLUDE_PATH
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string
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default "src/soc/intel/broadwell/microcode"
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config MMCONF_BASE_ADDRESS
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hex
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@ -208,6 +207,62 @@ config SERIRQ_CONTINUOUS_MODE
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help
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If you set this option to y, the serial IRQ machine will be
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operated in continuous mode.
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config HAVE_ME_BIN
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bool "Add Intel Management Engine firmware"
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default y
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help
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The Intel processor in the selected system requires a special firmware
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for an integrated controller called Management Engine (ME). The ME
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firmware might be provided in coreboot's 3rdparty repository. If
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not and if you don't have the firmware elsewhere, you can still
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build coreboot without it. In this case however, you'll have to make
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sure that you don't overwrite your ME firmware on your flash ROM.
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config ME_BIN_PATH
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string "Path to management engine firmware"
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depends on HAVE_ME_BIN
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default "3rdparty/mainboard/$(MAINBOARDDIR)/me.bin"
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config HAVE_IFD_BIN
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bool
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default n
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config BUILD_WITH_FAKE_IFD
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bool "Build with a fake IFD"
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default y if !HAVE_IFD_BIN
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help
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If you don't have an Intel Firmware Descriptor (ifd.bin) for your
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board, you can select this option and coreboot will build without it.
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Though, the resulting coreboot.rom will not contain all parts required
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to get coreboot running on your board. You can however write only the
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BIOS section to your board's flash ROM and keep the other sections
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untouched. Unfortunately the current version of flashrom doesn't
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support this yet. But there is a patch pending [1].
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WARNING: Never write a complete coreboot.rom to your flash ROM if it
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was built with a fake IFD. It just won't work.
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[1] http://www.flashrom.org/pipermail/flashrom/2013-June/011083.html
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config IFD_BIOS_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_ME_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_PLATFORM_SECTION
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depends on BUILD_WITH_FAKE_IFD
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string
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default ""
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config IFD_BIN_PATH
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string "Path to intel firmware descriptor"
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depends on !BUILD_WITH_FAKE_IFD
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default "3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin"
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config ME_MBP_CLEAR_LATE
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bool "Defer wait for ME MBP Cleared"
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@ -13,7 +13,7 @@ ramstage-y += acpi.c
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ramstage-y += adsp.c
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ramstage-y += chip.c
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ramstage-y += cpu.c
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ramstage-y += elog.c
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ramstage-$(CONFIG_ELOG) += elog.c
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ramstage-y += finalize.c
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ramstage-y += gpio.c
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romstage-y += gpio.c
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@ -69,20 +69,38 @@ romstage-y += usbdebug.c
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smm-y += usbdebug.c
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endif
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INCLUDES += -Isrc/soc/intel/broadwell/
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CPPFLAGS_common += -Isrc/soc/intel/broadwell/
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# Run an intermediate step when producing coreboot.rom
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# that adds additional components to the final firmware
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# image outside of CBFS
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INTERMEDIATE := pch_add_me
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INTERMEDIATE := broadwell_add_me
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pch_add_me: $(obj)/coreboot.pre $(IFDTOOL)
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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IFD_BIN_PATH := $(objgenerated)/ifdfake.bin
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IFD_SECTIONS := $(addprefix -b ,$(CONFIG_IFD_BIOS_SECTION:"%"=%)) \
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$(addprefix -m ,$(CONFIG_IFD_ME_SECTION:"%"=%)) \
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$(addprefix -p ,$(CONFIG_IFD_PLATFORM_SECTION:"%"=%))
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else
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IFD_BIN_PATH := $(CONFIG_IFD_BIN_PATH)
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endif
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broadwell_add_me: $(obj)/coreboot.pre $(IFDTOOL) $(IFDFAKE)
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ifeq ($(CONFIG_BUILD_WITH_FAKE_IFD),y)
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printf "\n** WARNING **\n"
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printf "Coreboot will be built with a fake Intel Firmware Descriptor (IFD).\n"
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printf "Never write a complete coreboot.rom with a fake IFD to your board's\n"
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printf "flash ROM! Make sure that you only write valid flash regions.\n\n"
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printf " IFDFAKE Building a fake Intel Firmware Descriptor\n"
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$(IFDFAKE) $(IFD_SECTIONS) $(IFD_BIN_PATH)
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endif
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
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dd if=$(IFD_BIN_PATH) \
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of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1
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ifeq ($(CONFIG_HAVE_ME_BIN),y)
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printf " IFDTOOL me.bin -> coreboot.pre\n"
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$(objutil)/ifdtool/ifdtool \
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-i ME:3rdparty/mainboard/$(MAINBOARDDIR)/me.bin \
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-i ME:$(CONFIG_ME_BIN_PATH) \
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$(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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ifeq ($(CONFIG_LOCK_MANAGEMENT_ENGINE),y)
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@ -94,8 +112,9 @@ else
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$(objutil)/ifdtool/ifdtool -u $(obj)/coreboot.pre
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mv $(obj)/coreboot.pre.new $(obj)/coreboot.pre
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endif
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endif
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PHONY += pch_add_me
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PHONY += broadwell_add_me
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# If an MRC file is an ELF file determine the entry address and first loadable
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# section offset in the file. Subtract the offset from the entry address to
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@ -48,7 +48,7 @@ static void enable_rom_caching(void)
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disable_cache();
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/* Why only top 4MiB ? */
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set_var_mtrr(1, CACHE_ROM_BASE, CONFIG_CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
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set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT);
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enable_cache();
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/* Enable Variable MTRRs */
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@ -33,7 +33,7 @@ static struct device_operations pci_domain_ops = {
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.read_resources = &pci_domain_read_resources,
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.set_resources = &pci_domain_set_resources,
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.scan_bus = &pci_domain_scan_bus,
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.ops_pci_bus = &pci_ops_mmconf,
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.ops_pci_bus = &pci_bus_default_ops,
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};
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static struct device_operations cpu_bus_ops = {
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@ -36,7 +36,6 @@
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#include <cpu/x86/smm.h>
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#include <delay.h>
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#include <pc80/mc146818rtc.h>
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#include <usbdebug.h>
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#include <broadwell/cpu.h>
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#include <broadwell/msr.h>
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#include <broadwell/pci_devs.h>
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@ -718,7 +717,4 @@ void broadwell_init_cpus(device_t dev)
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/* Restore the default SMM region. */
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restore_default_smm_area(smm_save_area);
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/* Enable ROM caching if option was selected. */
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x86_mtrr_enable_rom_caching();
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}
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@ -23,7 +23,6 @@
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/pci_ids.h>
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#include <usbdebug.h>
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#include <arch/io.h>
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#include <broadwell/ehci.h>
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#include <broadwell/pch.h>
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@ -18,6 +18,7 @@
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*/
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#include <arch/io.h>
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#include <bootmode.h>
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#include <console/console.h>
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#include <delay.h>
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#include <device/device.h>
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@ -472,7 +473,6 @@ static void igd_init(struct device *dev)
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{
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int is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT);
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u32 rp1_gfx_freq;
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extern int oprom_is_loaded;
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/* IGD needs to be Bus Master */
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u32 reg32 = pci_read_config32(dev, PCI_COMMAND);
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@ -512,7 +512,7 @@ static void igd_init(struct device *dev)
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reg_script_run_on_dev(dev, haswell_late_init_script);
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}
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if (!oprom_is_loaded) {
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if (!gfx_get_init_done()) {
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/*
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* Enable DDI-A if the Option ROM did not execute:
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*
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@ -525,25 +525,8 @@ static void igd_init(struct device *dev)
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}
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}
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static void igd_read_resources(struct device *dev)
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{
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pci_dev_read_resources(dev);
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#if CONFIG_MARK_GRAPHICS_MEM_WRCOMB
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struct resource *res;
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/* Set the graphics memory to write combining. */
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res = find_resource(dev, PCI_BASE_ADDRESS_2);
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if (res == NULL) {
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printk(BIOS_DEBUG, "gma: memory resource not found.\n");
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return;
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}
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res->flags |= IORESOURCE_WRCOMB;
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#endif
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}
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static struct device_operations igd_ops = {
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.read_resources = &igd_read_resources,
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.read_resources = &pci_dev_read_resources,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &igd_init,
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@ -19,7 +19,6 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <cpu/x86/stack.h>
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#include <cpu/x86/mtrr.h>
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#include <cpu/x86/cache.h>
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#include <cpu/x86/post_code.h>
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@ -85,7 +85,7 @@ void raminit(struct pei_data *pei_data)
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/* Determine if mrc.bin is in the cbfs. */
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entry = (pei_wrapper_entry_t)cbfs_get_file_content(
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CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab);
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CBFS_DEFAULT_MEDIA, "mrc.bin", 0xab, NULL);
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if (entry == NULL) {
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printk(BIOS_DEBUG, "Couldn't find mrc.bin\n");
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return;
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@ -31,7 +31,6 @@
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#include <ramstage_cache.h>
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#include <romstage_handoff.h>
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#include <timestamp.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <broadwell/me.h>
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#include <broadwell/pei_data.h>
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#include <broadwell/pm.h>
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@ -39,6 +38,20 @@
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#include <broadwell/romstage.h>
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#include <broadwell/spi.h>
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static inline uint64_t timestamp_get(void)
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{
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return rdtscll();
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}
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static inline tsc_t ts64_to_tsc(uint64_t ts)
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{
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tsc_t tsc = {
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.lo = ts,
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.hi = ts >> 32,
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};
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return tsc;
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}
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static inline void mark_ts(struct romstage_params *rp, uint64_t ts)
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{
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struct romstage_timestamps *rt = &rp->ts;
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@ -129,19 +142,16 @@ void romstage_common(struct romstage_params *params)
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chromeos_init(params->power_state->prev_sleep_state);
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/* Save timestamp information. */
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timestamp_init(params->ts.times[0]);
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timestamp_add(TS_START_ROMSTAGE, params->ts.times[1]);
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timestamp_add(TS_BEFORE_INITRAM, params->ts.times[2]);
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timestamp_add(TS_AFTER_INITRAM, params->ts.times[3]);
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timestamp_init(ts64_to_tsc(params->ts.times[0]));
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timestamp_add(TS_START_ROMSTAGE, ts64_to_tsc(params->ts.times[1]));
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timestamp_add(TS_BEFORE_INITRAM, ts64_to_tsc(params->ts.times[2]));
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timestamp_add(TS_AFTER_INITRAM, ts64_to_tsc(params->ts.times[3]));
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}
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void asmlinkage romstage_after_car(void)
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{
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timestamp_add_now(TS_END_ROMSTAGE);
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/* Run vboot verification if configured. */
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vboot_verify_firmware(romstage_handoff_find_or_add());
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/* Load the ramstage. */
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copy_and_run();
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while (1);
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@ -30,8 +30,6 @@
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#include <spi-generic.h>
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#include <broadwell/pci_devs.h>
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#define min(a, b) ((a)<(b)?(a):(b))
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#ifdef __SMM__
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#define pci_read_config_byte(dev, reg, targ)\
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*(targ) = pci_read_config8(dev, reg)
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@ -488,6 +486,11 @@ static int ich_status_poll(u16 bitmask, int wait_til_set)
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return -1;
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}
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unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len)
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{
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return min(cntlr.databytes, buf_len);
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}
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int spi_xfer(struct spi_slave *slave, const void *dout,
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unsigned int bytesout, void *din, unsigned int bytesin)
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{
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@ -588,7 +591,8 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
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while (trans.bytesout || trans.bytesin) {
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uint32_t data_length;
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/* SPI addresses are 24 bit only */http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf
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/* SPI addresses are 24 bit only */
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/* http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-n3520-j2850-celeron-n2920-n2820-n2815-n2806-j1850-j1750-datasheet.pdf */
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writel_(trans.offset & 0x00FFFFFF, cntlr.addr);
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if (trans.bytesout)
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@ -65,29 +65,3 @@ static inline void *spi_mirror(void *file_start, int file_len)
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/* Provide pointer into mirrored space. */
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return &dest[alignment_diff];
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}
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void *cbfs_load_payload(struct cbfs_media *media, const char *name)
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{
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int file_len;
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void *file_start;
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struct cbfs_file *file;
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file_start = vboot_get_payload(&file_len);
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if (file_start != NULL)
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return spi_mirror(file_start, file_len);
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file = cbfs_get_file(media, name);
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if (file == NULL)
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return NULL;
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if (ntohl(file->type) != CBFS_TYPE_PAYLOAD)
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return NULL;
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file_len = ntohl(file->len);
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file_start = CBFS_SUBHEADER(file);
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return spi_mirror(file_start, file_len);
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}
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@ -446,13 +446,13 @@ unsigned long acpi_fill_srat(unsigned long current)
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}
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static struct device_operations systemagent_ops = {
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.read_resources = systemagent_read_resources,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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.set_resources = pci_dev_set_resources,
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.enable_resources = pci_dev_enable_resources,
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.init = systemagent_init,
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.enable = systemagent_enable,
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.ops_pci = broadwell_pci_ops,
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.read_resources = &systemagent_read_resources,
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.acpi_fill_ssdt_generator = &generate_cpu_entries,
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.set_resources = &pci_dev_set_resources,
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.enable_resources = &pci_dev_enable_resources,
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.init = &systemagent_init,
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.enable = &systemagent_enable,
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.ops_pci = &broadwell_pci_ops,
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};
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static const unsigned short systemagent_ids[] = {
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