From a63f859553a29842fd8d65ae8a6523cd429a5f85 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 24 Mar 2023 16:30:55 +0100 Subject: [PATCH] soc/amd/common/cpu/tsc: factor out family-specific get_pstate_core_freq Factor out the get_pstate_core_freq function from the SoC's acpi.c files to both avoid duplication and to also be able to use the same function in the TSC frequency calculation in a follow-up patch. The family 17h and 19h SoCs use the same frequency encoding in the P state MSRs while the family 1Ah SoCs use a different encoding. The family 15h and 16h SoCs use another encoding, but since this isn't implemented in Stoneyridge's acpi.c, this will be added in a follow-up patch. Signed-off-by: Felix Held Change-Id: I8619822c2c61e06ae5db86896d5323c9b105b25b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74010 Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: Martin Roth --- src/soc/amd/cezanne/Kconfig | 1 + src/soc/amd/cezanne/acpi.c | 39 --------------- src/soc/amd/cezanne/include/soc/msr.h | 5 -- src/soc/amd/common/block/cpu/Kconfig | 12 +++++ src/soc/amd/common/block/cpu/tsc/Makefile.inc | 16 +++++++ .../amd/common/block/cpu/tsc/cpufreq_17_19.c | 48 +++++++++++++++++++ src/soc/amd/common/block/cpu/tsc/cpufreq_1a.c | 18 +++++++ src/soc/amd/glinda/Kconfig | 1 + src/soc/amd/glinda/acpi.c | 13 ----- src/soc/amd/glinda/include/soc/msr.h | 2 - src/soc/amd/mendocino/Kconfig | 1 + src/soc/amd/mendocino/acpi.c | 39 --------------- src/soc/amd/mendocino/include/soc/msr.h | 5 -- src/soc/amd/phoenix/Kconfig | 1 + src/soc/amd/phoenix/acpi.c | 39 --------------- src/soc/amd/phoenix/include/soc/msr.h | 5 -- src/soc/amd/picasso/Kconfig | 1 + src/soc/amd/picasso/acpi.c | 39 --------------- src/soc/amd/picasso/include/soc/msr.h | 5 -- 19 files changed, 99 insertions(+), 191 deletions(-) create mode 100644 src/soc/amd/common/block/cpu/tsc/cpufreq_17_19.c create mode 100644 src/soc/amd/common/block/cpu/tsc/cpufreq_1a.c diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index dbb628bfff..837fef866d 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -39,6 +39,7 @@ config SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_GRAPHICS diff --git a/src/soc/amd/cezanne/acpi.c b/src/soc/amd/cezanne/acpi.c index e883009e27..b8ac827896 100644 --- a/src/soc/amd/cezanne/acpi.c +++ b/src/soc/amd/cezanne/acpi.c @@ -13,11 +13,9 @@ #include #include #include -#include #include #include #include -#include #include #include "chip.h" @@ -95,43 +93,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ } -uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) -{ - uint32_t core_freq, core_freq_mul, core_freq_div; - bool valid_freq_divisor; - - /* Core frequency multiplier */ - core_freq_mul = pstate_reg.cpu_fid_0_7; - - /* Core frequency divisor ID */ - core_freq_div = pstate_reg.cpu_dfs_id; - - if (core_freq_div == 0) { - return 0; - } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN) - && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) { - /* Allow 1/8 integer steps for this range */ - valid_freq_divisor = true; - } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX) - && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { - /* Only allow 1/4 integer steps for this range */ - valid_freq_divisor = true; - } else { - valid_freq_divisor = false; - } - - if (valid_freq_divisor) { - /* 25 * core_freq_mul / (core_freq_div / 8) */ - core_freq = - ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); - } else { - printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", - core_freq_div); - core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul); - } - return core_freq; -} - const acpi_cstate_t cstate_cfg_table[] = { [0] = { .ctype = 1, diff --git a/src/soc/amd/cezanne/include/soc/msr.h b/src/soc/amd/cezanne/include/soc/msr.h index 79ebc7eee5..0fba3e6d83 100644 --- a/src/soc/amd/cezanne/include/soc/msr.h +++ b/src/soc/amd/cezanne/include/soc/msr.h @@ -17,11 +17,6 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_FREQ_DIV_MIN 0x8 -#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A -#define PSTATE_DEF_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_CORE_FREQ_BASE 25 - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index 5dc846bb00..391e1e5b35 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -39,6 +39,18 @@ config ACPI_CPU_STRING endif # SOC_AMD_COMMON_BLOCK_NONCAR +config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H + bool + help + Select this option to include code to calculate the CPU frequency + from the P state MSR values on AMD CPU families 17h and 19h. + +config SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH + bool + help + Select this option to include code to calculate the CPU frequency + from the P state MSR values on AMD CPU family 1Ah. + config SOC_AMD_COMMON_BLOCK_MCA_COMMON bool help diff --git a/src/soc/amd/common/block/cpu/tsc/Makefile.inc b/src/soc/amd/common/block/cpu/tsc/Makefile.inc index ba7f942c0b..6176023223 100644 --- a/src/soc/amd/common/block/cpu/tsc/Makefile.inc +++ b/src/soc/amd/common/block/cpu/tsc/Makefile.inc @@ -1,4 +1,20 @@ ## SPDX-License-Identifier: GPL-2.0-only + +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c + +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c + +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c + +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c + +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H) += cpufreq_17_19.c +smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH) += cpufreq_1a.c + ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_TSC_FAM17H_19H),y) bootblock-y += tsc_freq.c diff --git a/src/soc/amd/common/block/cpu/tsc/cpufreq_17_19.c b/src/soc/amd/common/block/cpu/tsc/cpufreq_17_19.c new file mode 100644 index 0000000000..8f5e3012d1 --- /dev/null +++ b/src/soc/amd/common/block/cpu/tsc/cpufreq_17_19.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#define PSTATE_DEF_FREQ_DIV_MIN 0x8 +#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A +#define PSTATE_DEF_FREQ_DIV_MAX 0x3E +#define PSTATE_DEF_CORE_FREQ_BASE 25 + +uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) +{ + uint32_t core_freq, core_freq_mul, core_freq_div; + bool valid_freq_divisor; + + /* Core frequency multiplier */ + core_freq_mul = pstate_reg.cpu_fid_0_7; + + /* Core frequency divisor ID */ + core_freq_div = pstate_reg.cpu_dfs_id; + + if (core_freq_div == 0) { + return 0; + } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN) + && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) { + /* Allow 1/8 integer steps for this range */ + valid_freq_divisor = true; + } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX) + && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { + /* Only allow 1/4 integer steps for this range */ + valid_freq_divisor = true; + } else { + valid_freq_divisor = false; + } + + if (valid_freq_divisor) { + /* 25 * core_freq_mul / (core_freq_div / 8) */ + core_freq = + ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); + } else { + printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", + core_freq_div); + core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul); + } + return core_freq; +} diff --git a/src/soc/amd/common/block/cpu/tsc/cpufreq_1a.c b/src/soc/amd/common/block/cpu/tsc/cpufreq_1a.c new file mode 100644 index 0000000000..c8cb59a37e --- /dev/null +++ b/src/soc/amd/common/block/cpu/tsc/cpufreq_1a.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define PSTATE_DEF_CORE_FREQ_BASE 5 + +uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) +{ + uint32_t core_freq_mul; + + /* Core frequency multiplier */ + core_freq_mul = pstate_reg.cpu_fid_0_11; + + /* CPU frequency is 5 * core_freq_mul */ + return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul; +} diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 5e9b7f95bb..c68ee47b00 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -44,6 +44,7 @@ config SOC_AMD_GLINDA select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS # TODO: Check if this is still correct + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM1AH select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_EMMC # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES # TODO: Check if this is still correct diff --git a/src/soc/amd/glinda/acpi.c b/src/soc/amd/glinda/acpi.c index 850bc6c5af..49fb658d63 100644 --- a/src/soc/amd/glinda/acpi.c +++ b/src/soc/amd/glinda/acpi.c @@ -16,11 +16,9 @@ #include #include #include -#include #include #include #include -#include #include #include "chip.h" @@ -98,17 +96,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ } -uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) -{ - uint32_t core_freq_mul; - - /* Core frequency multiplier */ - core_freq_mul = pstate_reg.cpu_fid_0_11; - - /* CPU frequency is 5 * core_freq_mul */ - return PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul; -} - const acpi_cstate_t cstate_cfg_table[] = { [0] = { .ctype = 1, diff --git a/src/soc/amd/glinda/include/soc/msr.h b/src/soc/amd/glinda/include/soc/msr.h index ad4d9d0445..2f40d395f3 100644 --- a/src/soc/amd/glinda/include/soc/msr.h +++ b/src/soc/amd/glinda/include/soc/msr.h @@ -20,8 +20,6 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_CORE_FREQ_BASE 5 - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/mendocino/Kconfig b/src/soc/amd/mendocino/Kconfig index 2df289f6d2..54b62c2cf7 100644 --- a/src/soc/amd/mendocino/Kconfig +++ b/src/soc/amd/mendocino/Kconfig @@ -43,6 +43,7 @@ config SOC_AMD_REMBRANDT_BASE select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_EMMC select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES diff --git a/src/soc/amd/mendocino/acpi.c b/src/soc/amd/mendocino/acpi.c index 6c48bae062..83b24ece7d 100644 --- a/src/soc/amd/mendocino/acpi.c +++ b/src/soc/amd/mendocino/acpi.c @@ -15,11 +15,9 @@ #include #include #include -#include #include #include #include -#include #include #include "chip.h" @@ -97,43 +95,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ } -uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) -{ - uint32_t core_freq, core_freq_mul, core_freq_div; - bool valid_freq_divisor; - - /* Core frequency multiplier */ - core_freq_mul = pstate_reg.cpu_fid_0_7; - - /* Core frequency divisor ID */ - core_freq_div = pstate_reg.cpu_dfs_id; - - if (core_freq_div == 0) { - return 0; - } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN) - && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) { - /* Allow 1/8 integer steps for this range */ - valid_freq_divisor = true; - } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX) - && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { - /* Only allow 1/4 integer steps for this range */ - valid_freq_divisor = true; - } else { - valid_freq_divisor = false; - } - - if (valid_freq_divisor) { - /* 25 * core_freq_mul / (core_freq_div / 8) */ - core_freq = - ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); - } else { - printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", - core_freq_div); - core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul); - } - return core_freq; -} - const acpi_cstate_t cstate_cfg_table[] = { [0] = { .ctype = 1, diff --git a/src/soc/amd/mendocino/include/soc/msr.h b/src/soc/amd/mendocino/include/soc/msr.h index b83997a029..cfc7702c9f 100644 --- a/src/soc/amd/mendocino/include/soc/msr.h +++ b/src/soc/amd/mendocino/include/soc/msr.h @@ -18,11 +18,6 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_FREQ_DIV_MIN 0x8 -#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A -#define PSTATE_DEF_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_CORE_FREQ_BASE 25 - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/phoenix/Kconfig b/src/soc/amd/phoenix/Kconfig index 96a287cf7f..bd2beccd27 100644 --- a/src/soc/amd/phoenix/Kconfig +++ b/src/soc/amd/phoenix/Kconfig @@ -44,6 +44,7 @@ config SOC_AMD_PHOENIX select SOC_AMD_COMMON_BLOCK_APOB # TODO: Check if this is still correct select SOC_AMD_COMMON_BLOCK_APOB_HASH select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_ESPI_EXTENDED_DECODE_RANGES select SOC_AMD_COMMON_BLOCK_GRAPHICS # TODO: Check if this is still correct diff --git a/src/soc/amd/phoenix/acpi.c b/src/soc/amd/phoenix/acpi.c index c98ec680b8..8e90d44c89 100644 --- a/src/soc/amd/phoenix/acpi.c +++ b/src/soc/amd/phoenix/acpi.c @@ -16,11 +16,9 @@ #include #include #include -#include #include #include #include -#include #include #include "chip.h" @@ -98,43 +96,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= cfg->common_config.fadt_flags; /* additional board-specific flags */ } -uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) -{ - uint32_t core_freq, core_freq_mul, core_freq_div; - bool valid_freq_divisor; - - /* Core frequency multiplier */ - core_freq_mul = pstate_reg.cpu_fid_0_7; - - /* Core frequency divisor ID */ - core_freq_div = pstate_reg.cpu_dfs_id; - - if (core_freq_div == 0) { - return 0; - } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN) - && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) { - /* Allow 1/8 integer steps for this range */ - valid_freq_divisor = true; - } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX) - && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { - /* Only allow 1/4 integer steps for this range */ - valid_freq_divisor = true; - } else { - valid_freq_divisor = false; - } - - if (valid_freq_divisor) { - /* 25 * core_freq_mul / (core_freq_div / 8) */ - core_freq = - ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); - } else { - printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", - core_freq_div); - core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul); - } - return core_freq; -} - const acpi_cstate_t cstate_cfg_table[] = { [0] = { .ctype = 1, diff --git a/src/soc/amd/phoenix/include/soc/msr.h b/src/soc/amd/phoenix/include/soc/msr.h index 173ee0999b..7acf3219b8 100644 --- a/src/soc/amd/phoenix/include/soc/msr.h +++ b/src/soc/amd/phoenix/include/soc/msr.h @@ -20,11 +20,6 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_FREQ_DIV_MIN 0x8 -#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A -#define PSTATE_DEF_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_CORE_FREQ_BASE 25 - #define MSR_CPPC_CAPABILITY_1 0xc00102b0 #define SHIFT_CPPC_CAPABILITY_1_HIGHEST_PERF 24 #define SHIFT_CPPC_CAPABILITY_1_NOMINAL_PERF 16 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 746b4fb87d..d59444c868 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -36,6 +36,7 @@ config SOC_AMD_PICASSO select SOC_AMD_COMMON_BLOCK_AOAC select SOC_AMD_COMMON_BLOCK_APOB select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS + select SOC_AMD_COMMON_BLOCK_CPUFREQ_FAM17H_19H select SOC_AMD_COMMON_BLOCK_DATA_FABRIC select SOC_AMD_COMMON_BLOCK_GRAPHICS select SOC_AMD_COMMON_BLOCK_HAS_ESPI diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 2379d4347b..a6f1ebd4e4 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -23,7 +22,6 @@ #include #include #include -#include #include #include #include "chip.h" @@ -99,43 +97,6 @@ void acpi_fill_fadt(acpi_fadt_t *fadt) fadt->flags |= cfg->fadt_flags; /* additional board-specific flags */ } -uint32_t get_pstate_core_freq(union pstate_msr pstate_reg) -{ - uint32_t core_freq, core_freq_mul, core_freq_div; - bool valid_freq_divisor; - - /* Core frequency multiplier */ - core_freq_mul = pstate_reg.cpu_fid_0_7; - - /* Core frequency divisor ID */ - core_freq_div = pstate_reg.cpu_dfs_id; - - if (core_freq_div == 0) { - return 0; - } else if ((core_freq_div >= PSTATE_DEF_FREQ_DIV_MIN) - && (core_freq_div <= PSTATE_DEF_EIGHTH_STEP_MAX)) { - /* Allow 1/8 integer steps for this range */ - valid_freq_divisor = true; - } else if ((core_freq_div > PSTATE_DEF_EIGHTH_STEP_MAX) - && (core_freq_div <= PSTATE_DEF_FREQ_DIV_MAX) && !(core_freq_div & 0x1)) { - /* Only allow 1/4 integer steps for this range */ - valid_freq_divisor = true; - } else { - valid_freq_divisor = false; - } - - if (valid_freq_divisor) { - /* 25 * core_freq_mul / (core_freq_div / 8) */ - core_freq = - ((PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul * 8) / (core_freq_div)); - } else { - printk(BIOS_WARNING, "Undefined core_freq_div %x used. Force to 1.\n", - core_freq_div); - core_freq = (PSTATE_DEF_CORE_FREQ_BASE * core_freq_mul); - } - return core_freq; -} - const acpi_cstate_t cstate_cfg_table[] = { [0] = { .ctype = 1, diff --git a/src/soc/amd/picasso/include/soc/msr.h b/src/soc/amd/picasso/include/soc/msr.h index 0747b847e3..ce84eecce1 100644 --- a/src/soc/amd/picasso/include/soc/msr.h +++ b/src/soc/amd/picasso/include/soc/msr.h @@ -21,9 +21,4 @@ union pstate_msr { uint64_t raw; }; -#define PSTATE_DEF_FREQ_DIV_MIN 0x8 -#define PSTATE_DEF_EIGHTH_STEP_MAX 0x1A -#define PSTATE_DEF_FREQ_DIV_MAX 0x3E -#define PSTATE_DEF_CORE_FREQ_BASE 25 - #endif /* AMD_PICASSO_MSR_H */