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soc/amd/common/block/gpio: remove SoC type check in gpio_fill_wake_state 

Verified that all accessed registers exist in all SoCs that use this
code (Carrizo, Mullins, Stoneyridge, Picasso and Cezanne at the moment)
and that the bit definitions match as well. Also at the time of writing
this patch only Picasso calls gpio_fill_wake_state, so dropping the
check won't change behavior. This also avoids having SoC specific code
that doesn't get selected by Kconfig options in the common AMD SoC
directory and also avoids having to add a check for SOC_AMD_CEZANNE to
support this functionality on Cezanne in a follow-up patch.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: If770780a67776daf81744db1b635ffd402653a47
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52223
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2021-04-09 20:53:19 +02:00 committed by Patrick Georgi
parent 70d1c723f7
commit a643e212c2
1 changed files with 0 additions and 4 deletions
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4
src/soc/amd/common/block/gpio_banks/gpio.c
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@ -347,10 +347,6 @@ void gpio_fill_wake_state(struct gpio_wake_state *state)
const uint8_t stat1 = GPIO_WAKE_STAT_1 / sizeof(uint32_t);
const uint8_t control_switch = GPIO_MASTER_SWITCH / sizeof(uint32_t);
/* Register fields and gpio availability need to be confirmed on other chipsets. */
if (!CONFIG(SOC_AMD_PICASSO))
dead_code();
memset(state, 0, sizeof(*state));
state->control_switch = gpio_read32(control_switch);